PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 41

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

External Reset Input
At the RST input an external reset can be applied forcing the Q-SMINT I in the reset
state. This external reset signal is additionally fed to the RSTO output.
After release of an external reset, the C has to wait for min. t
write access to the Q-SMINT I (see
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
t
Reset Generation
The Q-SMINT I has an on-chip reset generator based on a Power-On Reset (POR) and
Under Voltage Detection (UVD) circuit (see
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on V
Chapter
Clocks and Data Lines During Reset
During reset the data clock (DCL), the bit clock (BCL), the microcontroller clock
and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD IOM -2 channel 0 is ’DR’ = 0000
• The output C/I code from the S-Transceiver on DU IOM -2 channel 1 is ’TIM’ = 0000.
1)
Data Sheet
DEACT
(Value after reset of register UCIR = ’00
during a Power-On/UVD Reset, the microcontroller clock MCLK is not running, but starts running as soon as
timer t
(see
DEAC
5.6.5.
is started.
Table
41).
DD
ramp-up during power-on reset are described in
Table
H
27
40).
’)
Table
41). The POR/UVD requires no
Functional Description
C
before it starts read or
PEF 82912/82913
2001-03-30
1)
(MCLK)