Z16M1720ASG1868 Zilog, Z16M1720ASG1868 Datasheet - Page 44

• Manufacturer Part Number: Z16M1720ASG1868
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z16M1720ASG1868

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
CTC Counting and Timing
CS0. CS1, CE
Figure 10.
Figure 11 illustrates the timing diagram for the CTC Counting and Timing
modes.
In the Counter mode, the edge (rising edge is active in this example) from
the external hardware connected to pin CLK/TRG, decrements the down-
counter in synchronization with the System Clock Φ. This CLK/TRG pulse
must have a minimum width and the minimum period must not be less than
twice the System clock period. Although there is no setup time requirement
between the active edge of the CLK/TRG and the rising edge of Φ, if the
CLK/TRG edge occurs closer than a specified minimum time, the
decrement of the down-counter will be delayed one cycle of Φ.
Immediately after the 1 to 0 decrement of the down-counter, the ZC/TO
output is pulsed true.
In the Timer mode, a pulse trigger (user selectable as either active High or
active Low) at the CLK/TRG pin enables the timing function on the second
succeeding rising edge of Φ. As in the Counter mode, the triggering pulse is
DATA
IORQ
CLK
RD
M1
CTC Read Cycle
T
1
T
2
Channel Address
T
WA
OUT
T
3
Counter/Timer Channels
T
1