Z16M1720ASG1868 Zilog, Z16M1720ASG1868 Datasheet - Page 275

• Manufacturer Part Number: Z16M1720ASG1868
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z16M1720ASG1868

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7. Bisync Receive Mode (Continued)
SDLC (HDLC) OPERATION
UM008101-0601
Function
Termination
Overview
The Z80 SIO allows processing of both High-level Synchronous Data
Link Control (HDLC) and IBM Synchronous Data Link Control (SDLC)
protocols. In this chapter only Synchronous Data Link Control (SDLC) is
covered because of the similarity between SDLC and HDLC.
The SDLC mode is bit oriented which differs from Synchronous Bisync
protocol, which is character oriented. Therefore, SDLC mode allows trans-
parent operation and variable message length. The bit-orientation SDLC is
a flexible protocol because it can process longer message length and bit
patterns. IBM document GA27-3093 has more information about SDLC
protocol.
The SDLC message, called the frame
flags that are similar to the sync characters in Bisync protocol. The Z80 SIO
handles the transmission and recognition of the flag characters that mark
the beginning and end of the frame. Although the Z80 SIO can receive
shared-zero flags, it cannot transmit them. The 8-bit address field of an
SDLC frame contains the secondary station address. The Z80 SIO has an
Address Search mode that recognizes the secondary station address,
allowing it to accept or reject the frame.
Typical Program Steps
Redefine Interrupt Modes and Sync
Modes
Update Modem Controls
Disables Receive Mode
(Figure
Comments
113), is opened and closed by
Z80 CPU Peripherals
Serial Input/Output
User Manual
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