F515C8EMCAXP Infineon Technologies, F515C8EMCAXP Datasheet - Page 78

• Manufacturer Part Number: F515C8EMCAXP
• Description: 8 BIT OTP
• Manufacturer: Infineon Technologies

Specifications of F515C8EMCAXP

• Cpu Family: C500
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 10MHz
• Interface Type: CAN/SPI/USART
• Program Memory Type: EPROM
• Program Memory Size: 64KB
• Total Internal Ram Size: 2.25KB
• # I/os (max): 49
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.25V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: MQFP
• Lead Free Status / Rohs Status: Compliant

A/D Converter Characteristics (Operating Conditions apply)
Parameter
Analog input voltage
Sample time
Conversion cycle time
Total unadjusted error
Internal resistance of
reference voltage source
Internal resistance of
analog source
ADC input capacitance
1)
2)
3)
4)
5)
6)
Data Sheet
V
these cases will be X000
During the sample time the input capacitance
internal resistance of the analog source must allow the capacitance to reach their final voltage level within
After the end of the sample time
This parameter includes the sample time
calibration. Values for the conversion clock
the previous page.
T
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
Not 100% tested, but guaranteed by design characterization.
UE
AIN
is tested at
may exceed
V
AREF
V
AGND
= 5.0 V,
H
or
or X3FF
V
AREF
Symbol
V
t
t
T
R
R
C
t
S
ADCC
V
S
UE
AIN
AREF
ASRC
AIN
, changes of the analog input voltage have no effect on the conversion result.
AGND
H
up to the absolute maximum ratings. However, the conversion result in
, respectively.
= 0 V,
t
S
t
min.
V
–
–
–
–
–
–
ADC
, the time for determining the digital result and the time for the
AGND
V
C
DD
AIN
depend on programming and can be taken from the table on
Limit Values
= 4.9 V. It is guaranteed by design characterization for all
74
can be charged/discharged by the external source. The
max.
V
16
8
96
48
t
- 0.25
t
- 0.25
50
ADC
S
2
AREF
/ 500
t
IN
t
t
t
/ 250
IN
IN
IN
Unit Test Condition
V
ns
ns
LSB
k
k
pF
1)
Prescaler
Prescaler
Prescaler
Prescaler
4)
t
t
6)
ADC
S
in [ns]
in [ns]
2)6)
5)6)
8
4
8
4
C515C
2003-02
2)
3)
t
S
.