F515C8EMCAXP Infineon Technologies, F515C8EMCAXP Datasheet - Page 33

• Manufacturer Part Number: F515C8EMCAXP
• Description: 8 BIT OTP
• Manufacturer: Infineon Technologies

Specifications of F515C8EMCAXP

• Cpu Family: C500
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 10MHz
• Interface Type: CAN/SPI/USART
• Program Memory Type: EPROM
• Program Memory Size: 64KB
• Total Internal Ram Size: 2.25KB
• # I/os (max): 49
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.25V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: MQFP
• Lead Free Status / Rohs Status: Compliant

Table 5
Addr. Register
D0
D8
D9
DA
DB
DC
E0
E8
F0
F8
F8
FA
FC
FD
FE
1)
2)
3)
4)
5)
6)
7)
8)
9)
Data Sheet
H
H
H
H
H
H
H
H
H
H
H
H
“X” means that the value is undefined and the location is reserved.
Bit-addressable special function registers
SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
This SFR is available in the C515C-8R and C515C-L.
This SFR is available in the C515C-8E.
This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.
This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
These SFRs are read-only registers (C515C-8E only).
The content of this SFR varies with the actual step of the C515C-8E (e.g. 01
H
H
H
2)
2)
2)
2)
2)
2)
2)
PSW
ADCON0
ADDATH
ADDATL
P6
ADCON1
ACC
P4
B
P5
DIR5
P7
VR0
VR1
VR2
7)8)
7)8)
7)8)
6)
Contents of the SFRs, SFRs in Numeric Order
of their Addresses (cont’d)
Content
after
Reset
00
00
00
00XX-
XXXX
–
0XXX-
X000
00
FF
00
FF
FF
XXXX-
XXX1
C5
95
02
H
H
H
H
H
H
H
H
H
H
H
9)
B
B
B
1)
Bit 7
CY
BD
.9
.1
.7
ADCL
.7
RXDC
.7
.7
.7
–
1
1
0
Bit 6
AC
CLK
.8
.0
.6
–
.6
TXDC
.6
.6
.6
–
1
0
0
Bit 5
F0
ADEX
.7
–
.5
–
.5
INT8
.5
.5
.5
–
0
0
0
29
Bit 4
RS1
BSY
.6
–
.4
–
.4
SLS
.4
.4
.4
–
0
1
0
Bit 3
RS0
ADM
.5
–
.3
.3
STO
.3
.3
.3
–
0
0
0
0
H
for the first step).
Bit 2
OV
MX2
.4
–
.2
MX2
.2
SRI
.2
.2
.2
–
1
1
0
Bit 1
F1
MX1
.3
–
.1
MX1
.1
SCLK
.1
.1
.1
–
0
0
1
C515C
Bit 0
P
MX0
.2
–
.0
MX0
.0
ADST
.0
.0
.0
INT7
1
1
0
2003-02