F515C8EMCAXP Infineon Technologies, F515C8EMCAXP Datasheet - Page 22

• Manufacturer Part Number: F515C8EMCAXP
• Description: 8 BIT OTP
• Manufacturer: Infineon Technologies

Specifications of F515C8EMCAXP

• Cpu Family: C500
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 10MHz
• Interface Type: CAN/SPI/USART
• Program Memory Type: EPROM
• Program Memory Size: 64KB
• Total Internal Ram Size: 2.25KB
• # I/os (max): 49
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.25V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: MQFP
• Lead Free Status / Rohs Status: Compliant

C515C
The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR,
MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the
XRAM or CAN controller, the effective address stored in DPTR must be in the range of
F700
to FFFF
.
H
H
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX
@Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1).
Therefore, a special page register XPAGE which provides the upper address information
(A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX
access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the
state of pin
.
Table 3
lists the various operating conditions.
EA
Data Sheet
18
2003-02