F515C8EMCAXP Infineon Technologies, F515C8EMCAXP Datasheet - Page 47

• Manufacturer Part Number: F515C8EMCAXP
• Description: 8 BIT OTP
• Manufacturer: Infineon Technologies

Specifications of F515C8EMCAXP

• Cpu Family: C500
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 10MHz
• Interface Type: CAN/SPI/USART
• Program Memory Type: EPROM
• Program Memory Size: 64KB
• Total Internal Ram Size: 2.25KB
• # I/os (max): 49
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.25V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: MQFP
• Lead Free Status / Rohs Status: Compliant

Figure 17
The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the
parallel access to the whole data or remote frame for the acceptance match test and the
parallel transfer of the frame to and from the Intelligent Memory.
The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream
between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also
controls the EML and the parallel data stream between the TX/RX Shift Register and the
Intelligent Memory such that the processes of reception, arbitration, transmission, and
error signalling are performed according to the CAN protocol. Note that the automatic
retransmission of messages which have been corrupted by noise or other external error
conditions on the bus line is handled by the BSP.
Data Sheet
to internal Bus
CAN Controller Block Diagram
Messages
Handlers
Status +
Control
Interrupt
Register
Register
Status
TXDC
TX/RX Shift Register
BTL-Configuration
Processor
Intelligent
Memory
Stream
Bit
Messages
Gen./Check
CRC
43
RXDC
Timing
Logic
Bit
Management
Generator
Control
Timing
Clocks
(to all)
Logic
Error
MCB02736
C515C
2003-02