STM32W108HBU64TR STMicroelectronics, STM32W108HBU64TR Datasheet - Page 77

• Manufacturer Part Number: STM32W108HBU64TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU64TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
Note:
9.3.3
9.4
Every time an automatic character transmission starts, a transmit underrun is detected as
there is no data in transmit FIFO, and the INT_SCTXUND bit in the INT_SC2FLAG register
is set. After automatic character transmission is disabled, no more new characters are
received. The receive FIFO holds characters just received.
The Receive DMA complete event does not always mean the receive FIFO is empty.
The DMA Channels section describes how to configure and use the serial receive and
transmit DMA channels.
Interrupts
SPI master controller second level interrupts are generated by the following events:
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To enable CPU interrupts, set the desired interrupt bits in the second level INT_SCxCFG
register, and enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit in the
INT_CFGSET register.
SPI slave mode
Both SC1 and SC2 SPI controllers include a SPI slave controller with these features:
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The SPI slave controller uses four signals:
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The GPIO pins that can be assigned to these signals are shown in
Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE,
either the 0 to 1 transition or the high level of SC_SPITXIDLE)
Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0
to 1 transition or the high level of SC_SPITXFREE)
Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either
the 0 to 1 transition or the high level of SC_SPIRXVAL)
Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)
Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)
Received and lost character while receive FIFO was full (receive overrun error)
Transmitted character while transmit FIFO was empty (transmit underrun error)
Full duplex operation
Up to 5 Mbps data transfer rate
Programmable clock polarity and clock phase
Selectable data shift direction (either LSB or MSB first)
Slave select input
MOSI (Master Out, Slave In) - inputs serial data from the master
MISO (Master In, Slave Out) - outputs serial data to the master
SCLK (Serial Clock) - clocks data transfers on MOSI and MISO
nSSEL (Slave Select) - enables serial communication with the slave
Doc ID 16252 Rev 8
Table
15.
Serial interfaces
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