STM32W108HBU64TR STMicroelectronics, STM32W108HBU64TR Datasheet - Page 163

• Manufacturer Part Number: STM32W108HBU64TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU64TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
11.1.8
To convert multiple inputs using this approach, repeat Steps 4 through 6, loading the desired
input configurations to ADC_CFG in Step 5. If the inputs can use the same offset/gain
correction, just repeat Steps 5 and 6.
Calibration
Sampling of internal connections GND, VREF/2, and VREF allow for offset and gain
calibration of the ADC in applications where absolute accuracy is important. Offset error is
calculated from the minimum input and gain error is calculated from the full scale input
range. Correction using VREF is recommended because VREF is calibrated by the ST
software against VDD_PADSA. The VDD_PADSA regulator is factory-trimmed to 1.80 V ±
20 mV. If better absolute accuracy is required, the ADC can be configured to use an external
reference. The ADC calibrates as a single-ended measurement. Differential signals require
correction of both their inputs.
Table 31
Table 31.
Equation notes
●
●
●
●
●
Gain, buffer disabled
Gain, buffer enabled
Offset, buffer disabled (after applying gain correction)
Offset, buffer enabled (after applying gain correction)
All N are 16-bit two’s complement numbers.
N
the minimum two’s complement value 0x8000 as the conversion result. Instead, VGND
yields a two’s complement value close to 0xE000 when the input buffer is not selected.
VGND cannot be measured when the input buffer is enabled because it is outside the
buffer’s input range.
N
the maximum positive two’s complement 0x7FFF as the conversion result. Instead,
VREF yields a two’s complement value close to 0x2000 when the input buffer is not
selected and yields a two’s complement value close to 0xF000 when the input buffer is
selected.
N
0x0000 when the input buffer is not selected, and yields a two’s complement value
close to 0xE800 when the input buffer is selected.
Offset correction is affected by the gain correction value. Offset correction is calculated
after gain correction has been applied.
GND
VREF
VREF/2
shows the equations used to calculate the gain and offset correction values.
is a sampling of ground. Due to the ADC's internal design, VGND does not yield
is a sampling of VREF. Due to the ADC's internal design, VREF does not yield
ADC gain and offset correction equations
is a sampling of VREF/2. VREF/2 yields a two’s complement value close to
Calibration
Doc ID 16252 Rev 8
Analog-to-digital converter
Correction value
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