STM32W108HBU64TR STMicroelectronics, STM32W108HBU64TR Datasheet - Page 57

• Manufacturer Part Number: STM32W108HBU64TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU64TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
8.1.3
Note:
Table 6.
If a GPIO has two peripherals that can be the source of alternate output mode data, then
other registers in addition to GPIO_PxCFGH/L determine which peripheral controls the
output.
Several GPIOs share an alternate output with Timer 2 and the Serial Controllers. Bits in
Timer 2's TIM2_OR register control routing Timer 2 outputs to different GPIOs. Bits in Timer
2's TIM2_CCER register enable Timer 2 outputs. When Timer 2 outputs are enabled they
override Serial Controller outputs.
depending on the bits in the register TIM2_OR. Refer to
on page 106
Table 7.
For outputs assigned to the serial controllers, the serial interface mode registers
(SCx_MODE) determine how the GPIO pins are used.
The alternate outputs of PA4 and PA5 can either provide packet trace data (PTI_EN and
PTI_DATA), or synchronous CPU trace data (TRACEDATA2 and TRACEDATA3).
If a GPIO does not have an associated peripheral in alternate output mode, its output is set
to 0.
Forced functions
For some GPIOs the GPIO_PxCFGH/L configuration may be overridden.
GPIOs that can have different functions forced on them regardless of the GPIO_PxCFGH/L
registers.
The DEBUG_DIS bit in the GPIO_DBGCFG register can disable the Serial Wire/JTAG
debugger interface. When this bit is set, all debugger-related pins (PC0, PC2, PC3, PC4)
behave as standard GPIO.
Alternate Output (open-
drain)
Alternate Output (push-
pull) SPI SCLK Mode
Timer 2 output
GPIO mode
TIM2_CH1
TIM2_CH2
TIM2_CH3
TIM2_CH4
GPIO configuration modes (continued)
Timer 2 output configuration controls
for complete information on timer configuration.
0xD
0xB
GPIO_PxCFGH/L
Option register bit
TIM2_OR[4]
TIM2_OR[5]
TIM2_OR[6]
TIM2_OR[7]
Doc ID 16252 Rev 8
Table 7
Open-drain output. An onboard peripheral controls the
output. If a pull up is required, it must be external.
Push-pull output mode only for SPI master mode
SCLK pins.
indicates the GPIO mapping for Timer 2 outputs
GPIO mapping selected by TIM2_OR bit
Section 10: General-purpose timers
PA0
PA3
PA1
PA2
0
General-purpose input/outputs
Description
Table 8
PB1
PB2
PB3
PB4
1
shows the
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