PIC32MX675F512L-80V/BG Microchip Technology, PIC32MX675F512L-80V/BG Datasheet - Page 88
![512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX675F512L-80V/BG
Manufacturer Part Number
PIC32MX675F512L-80V/BG
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/BG
Processor Series
PIC32MX6xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
64 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
XBGA-100
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
-
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-19:
Legend:
Note
3060 DCH0CON
3070 DCH0ECON
3080
3090 DCH0SSA
30A0 DCH0DSA
30B0 DCH0SSIZ
30C0 DCH0DSIZ
30D0 DCH0SPTR
30E0 DCH0DPTR
30F0 DCH0CSIZ
3100 DCH0CPTR
3120 DCH1CON
3130 DCH1ECON
3140
3150 DCH1SSA
3160 DCH1DSA
3170 DCH1SSIZ
3110
1:
DCH0DAT
DCH0INT
DCH1INT
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
DMA CHANNELS 0-7 REGISTER MAP
CHBUSY
CHBUSY
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
—
—
—
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSIRQ<7:0>
—
—
—
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1,2)
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
CHCHNS
24/8
CHSPTR<15:0>
CHDPTR<15:0>
CHCPTR<15:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHCSIZ<15:0>
CHSSIZ<15:0>
CHSSA<31:0>
CHDSA<31:0>
CHSSA<31:0>
CHDSA<31:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
CFORCE
CFORCE
CHSDIE
CHSDIF
CHSDIE
CHSDIF
CHEN
CHEN
23/7
—
—
—
—
—
—
—
—
—
—
CABORT
CABORT
CHSHIE
CHSHIE
CHAED
CHSHIF
CHAED
CHSHIF
22/6
—
—
—
—
—
—
—
—
—
—
CHDDIE
CHDDIF
CHDDIE
CHDDIF
CHCHN
CHCHN
PATEN
PATEN
21/5
—
—
—
—
—
—
—
—
—
—
SIRQEN
CHDHIE
SIRQEN
CHDHIE
CHDHIF
CHDHIF
CHAEN
CHAEN
20/4
Section 12.1.1 “CLR, SET and INV Registers”
CHPDAT<7:0>
—
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
CHAIRQ<7:0>
—
AIRQEN
CHBCIE
CHBCIF
AIRQEN
CHBCIE
CHBCIF
19/3
—
—
—
—
—
—
—
—
—
—
—
—
CHEDET
CHEDET
CHCCIE
CHCCIF
CHCCIE
CHCCIF
18/2
—
—
—
—
—
—
—
—
—
—
—
—
CHTAIE
CHTAIF
CHTAIE
CHTAIF
17/1
—
—
—
—
—
—
—
—
—
—
—
—
CHPRI<1:0>
CHPRI<1:0>
CHERIE 0000
CHERIF
CHERIE 0000
CHERIF
for more
16/0
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
00FF
FF00
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
0000
0000
0000
0000
0000
0000
0000
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