PIC32MX675F512L-80V/BG Microchip Technology, PIC32MX675F512L-80V/BG Datasheet - Page 252
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PIC32MX675F512L-80V/BG
Manufacturer Part Number
PIC32MX675F512L-80V/BG
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/BG
Processor Series
PIC32MX6xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
64 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
XBGA-100
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
-
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX5XX/6XX/7XX
Parallel Master Port (PMP) ............................................... 149
PIC32 Family USB Interface Diagram............................... 132
Pinout I/O Descriptions (table) ............................................ 32
Power-on Reset (POR)
Power-Saving Features..................................................... 163
Prefetch Cache ................................................................. 127
Program Flash Memory
R
Reader Response ............................................................. 254
Real-Time Clock and Calendar (RTCC)............................ 151
Register Maps ............................................................. 62–116
Registers
Resets ............................................................................... 119
Revision History ................................................................ 240
S
Serial Peripheral Interface (SPI) ....................................... 143
Software Simulator (MPLAB SIM)..................................... 181
Special Features ............................................................... 165
T
Timer1 Module .................................................................. 135
Timer2/3, Timer4/5 Modules ............................................. 137
Timing Diagrams
DS61156G-page 252
Details ....................................................................... 227
Marking ..................................................................... 225
and On-Chip Voltage Regulator ................................ 174
CPU Halted Methods ................................................ 163
Operation .................................................................. 163
with CPU Running..................................................... 163
Wait State Characteristics......................................... 192
DDPCON (Debug Data Port Control)........................ 176
DEVCFG0 (Device Configuration Word 0 ................. 166
DEVCFG1 (Device Configuration Word 1 ................. 168
DEVCFG2 (Device Configuration Word 2 ................. 170
DEVCFG3 (Device Configuration Word 3 ................. 171
DEVID (Device and Revision ID) .............................. 172
10-bit Analog-to-Digital Conversion (ASAM = 0, SS-
10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01,
CAN I/O..................................................................... 212
EJTAG ...................................................................... 224
External Clock ........................................................... 194
RC<2:0> = 000) ................................................ 218
ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> =
00001)............................................................... 219
Timing Requirements
Timing Specifications
U
UART ................................................................................ 147
USB On-The-Go (OTG) .................................................... 131
V
V
Voltage Reference Specifications..................................... 193
Voltage Regulator (On-Chip) ............................................ 174
W
Watchdog Timer (WDT).................................................... 173
WWW Address ................................................................. 253
WWW, On-Line Support ..................................................... 29
CAP
I/O Characteristics .................................................... 197
I2Cx Bus Data (Master Mode) .................................. 208
I2Cx Bus Data (Slave Mode) .................................... 210
I2Cx Bus Start/Stop Bits (Master Mode)................... 208
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 210
Input Capture (CAPx) ............................................... 201
OCx/PWM................................................................. 202
Output Compare (OCx)............................................. 202
Parallel Master Port Read......................................... 221
Parallel Master Port Write......................................... 222
Parallel Slave Port .................................................... 220
SPIx Master Mode (CKE = 0) ................................... 203
SPIx Master Mode (CKE = 1) ................................... 204
SPIx Slave Mode (CKE = 0) ..................................... 205
SPIx Slave Mode (CKE = 1) ..................................... 206
Timer1, 2, 3, 4, 5 External Clock .............................. 200
UART Reception....................................................... 148
UART Transmission (8-bit or 9-bit Data) .................. 148
CLKO and I/O ........................................................... 197
CAN I/O Requirements ............................................. 212
I2Cx Bus Data Requirements (Master Mode)........... 209
I2Cx Bus Data Requirements (Slave Mode)............. 211
Input Capture Requirements..................................... 201
Output Compare Requirements................................ 202
Simple OCx/PWM Mode Requirements ................... 202
SPIx Master Mode (CKE = 0) Requirements............ 203
SPIx Master Mode (CKE = 1) Requirements............ 204
SPIx Slave Mode (CKE = 1) Requirements.............. 206
SPIx Slave Mode Requirements (CKE = 0).............. 205
/V
CORE
pin ................................................................ 174
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