PIC32MX675F512L-80V/BG Microchip Technology, PIC32MX675F512L-80V/BG Datasheet - Page 83
![512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX675F512L-80V/BG
Manufacturer Part Number
PIC32MX675F512L-80V/BG
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/BG
Processor Series
PIC32MX6xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
64 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
XBGA-100
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
-
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-14:
Legend:
Note
5800 SPI3CON
5810 SPI3STAT
5820
5830 SPI3BRG
5A00 SPI2CON
5A10 SPI2STAT
5A20
5A30 SPI2BRG
5C00 SPI4CON
5C10 SPI4STAT
5C20 SPI4BUF
5C30 SPI4BRG
1:
SPI3BUF
SPI2BUF
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
for more information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
SPI2, SPI3 AND SPI4 REGISTER MAP
FRMEN
FRMEN
FRMEN
31/15
ON
ON
ON
—
—
—
—
—
—
—
—
—
—
—
—
FRMSYNC FRMPOL
FRMSYNC FRMPOL
FRMSYNC FRMPOL
30/14
FRZ
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
DISSDO
DISSDO
DISSDO
MSSEN
MSSEN
MSSEN
28/12
—
—
—
—
—
—
—
—
—
FRMSYPW
FRMSYPW
FRMSYPW
SPIBUSY
SPIBUSY
SPIBUSY
MODE32
MODE32
MODE32
27/11
—
—
—
—
—
—
RXBUFELM<4:0>
RXBUFELM<4:0>
RXBUFELM<4:0>
(1)
MODE16
MODE16
MODE16
26/10
—
—
—
—
—
—
—
—
—
FRMCNT<2:0>
FRMCNT<2:0>
FRMCNT<2:0>
25/9
SMP
SMP
SMP
—
—
—
—
—
—
—
—
—
SPITUR
SPITUR
SPITUR
24/8
CKE
CKE
CKE
—
—
—
DATA<31:0>
DATA<31:0>
DATA<31:0>
Bits
SSEN
SRMT
SSEN
SRMT
SSEN
SRMT
23/7
—
—
—
—
—
—
—
—
—
SPIROV
SPIROV
SPIROV
22/6
CKP
CKP
CKP
—
—
—
—
—
—
—
—
—
SPIRBE
SPIRBE
SPIRBE
MSTEN
MSTEN
MSTEN
21/5
—
—
—
—
—
—
—
—
—
BRG<8:0>
BRG<8:0>
BRG<8:0>
20/4
—
—
—
—
—
—
—
—
—
—
—
—
SPITBE
SPITBE
SPITBE
19/3
STXISEL<1:0>
STXISEL<1:0>
STXISEL<1:0>
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
TXBUFELM<4:0>
TXBUFELM<4:0>
TXBUFELM<4:0>
18/2
—
—
—
—
—
—
—
—
—
SPITBF
SPITBF
SPITBF
SPIFE
SPIFE
SPIFE
17/1
SRXISEL<1:0>
SRXISEL<1:0>
SRXISEL<1:0>
—
—
—
ENHBUF 0000
ENHBUF 0000
ENHBUF 0000
SPIRBF
SPIRBF
SPIRBF
16/0
—
—
—
0000
0000
0008
0000
0000
0000
0000
0000
0000
0008
0000
0000
0000
0000
0000
0000
0008
0000
0000
0000
0000
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