PIC32MX675F512L-80V/BG Microchip Technology, PIC32MX675F512L-80V/BG Datasheet - Page 103
![512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX675F512L-80V/BG
Manufacturer Part Number
PIC32MX675F512L-80V/BG
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/BG
Processor Series
PIC32MX6xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
64 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
XBGA-100
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
-
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-38:
TABLE 4-39:
Legend:
Note
Legend:
F200 DDPCON
7000
7010 PMMODE
7020 PMADDR
7030 PMDOUT
7040
7050
7060
1:
PMSTAT
PMCON
PMAEN
PMDIN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0 CS2EN/A15 CS1EN/A14
15:0
15:0
15:0
15:0
PARALLEL MASTER PORT REGISTER MAP
PROGRAMMING AND DIAGNOSTICS REGISTER MAP
31/15
BUSY
31/15
ON
IBF
—
—
—
—
—
—
—
30/14
30/14
IBOV
FRZ
—
—
—
—
—
—
—
IRQM<1:0>
29/13
29/13
SIDL
—
—
—
—
—
—
—
—
28/12
28/12
ADRMUX<1:0>
—
—
—
—
—
—
—
—
INCM<1:0>
27/11
27/11
IB3F
—
—
—
—
—
—
—
PMPTTL
MODE16
26/10
26/10
IB2F
—
—
—
—
—
—
—
(1)
PTWREN
25/9
25/9
IB1F
—
—
—
—
—
—
—
MODE<1:0>
PTRDEN
24/8
DATAOUT<31:0>
24/8
IB0F
DATAIN<31:0>
—
—
—
—
—
—
—
PTEN<15:0>
Bits
Bits
23/7
23/7
OBE
—
—
—
—
—
—
—
ADDR<13:0>
WAITB<1:0>
CSF<1:0>
OBUF
22/6
22/6
—
—
—
—
—
—
—
21/5
21/5
ALP
—
—
—
—
—
—
—
—
CS2P
20/4
20/4
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
WAITM<3:0>
JTAGEN
CS1P
OB3E
19/3
19/3
—
—
—
—
—
—
TROEN
OB2E
18/2
18/2
—
—
—
—
—
—
—
WRSP
OB1E
17/1
17/1
—
—
—
—
—
—
—
WAITE<1:0>
TDOEN
RDSP
OB0E
16/0
for more
16/0
—
—
—
—
—
—
0000
0008
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
008F
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