PIC32MX675F512L-80V/BG Microchip Technology, PIC32MX675F512L-80V/BG Datasheet - Page 133
![512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX675F512L-80V/BG
Manufacturer Part Number
PIC32MX675F512L-80V/BG
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/BG
Processor Series
PIC32MX6xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
64 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
XBGA-100
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
-
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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12.0
FIGURE 12-1:
© 2009-2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
Legend:
Note:
2: Some registers and associated bits
I/O PORTS
PIO Module
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120)
Reference Manual” , which is available
from
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
R = Peripheral input buffer types may vary. Refer to
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
WR PORT
RD PORT
Peripheral Input
RD ODC
WR ODC
WR TRIS
Data Bus
RD TRIS
SYSCLK
SYSCLK
WR LAT
RD LAT
Sleep
the
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
in
Microchip
Peripheral Input Buffer
the
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Peripheral Module
“PIC32
web
D
D
D
CK
CK
CK
Family
EN Q
EN Q
EN Q
R
site
Q
Q
Q
in
Table 1-1
ODC
TRIS
LAT
0
1
for peripheral details.
Q
Output Multiplexers
Q
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
• Monitor selective inputs and generate interrupt
• Operation during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
Figure 12-1
multiplexed I/O port.
PIC32MX5XX/6XX/7XX
Synchronization
CK
when change in pin state is detected
registers
D
1
0
1
0
Q
Q
illustrates a block diagram of a typical
CK
D
0
1
®
MCU to monitor and control
I/O Cell
DS61156G-page 133
I/O Pin
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