PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 9

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.0
There are three memory blocks in the PIC16F872. The
Program Memory and Data Memory have separate
buses so that concurrent access can occur. Data mem-
ory is covered in this section; the EEPROM data mem-
ory and FLASH program memory blocks are detailed in
Section 3.0.
Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual
(DS33023).
2.1
The PIC16F872 has a 13-bit program counter capable
of addressing an 8K word x 14 bit program memory
space. The PIC16F872 device actually has 2K words of
FLASH program memory. Accessing a location above
the physically implemented address will cause a wrap-
around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1:
© 2006 Microchip Technology Inc.
Program
On-Chip
Memory
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
Interrupt Vector
PIC16F872 PROGRAM
MEMORY MAP AND
STACK
Stack Level 8
Stack Level 2
Reset Vector
Stack Level 1
PC<12:0>
Page 0
13
0000h
0004h
0005h
07FFh
1FFFh
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1
The register file can be accessed either directly, or indi-
rectly through the File Select Register (FSR).
Note:
RP1:RP0
Data Memory Organization
EEPROM Data Memory description can be
found in Section 4.0 of this data sheet.
GENERAL PURPOSE REGISTER
FILE
00
01
10
11
PIC16F872
DS30221C-page 7
Bank
0
1
2
3