PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 12

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F872
TABLE 2-1:
DS30221C-page 10
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
95h
95h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
Bank 1
(2)
(2)
(2)
(2)
(1,2)
(2)
2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
ADRESL
ADCON1
Shaded locations are unimplemented, read as ‘0’.
transferred to the upper byte of the program counter.
Name
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—
—
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—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low Byte
RBPU
GCEN
ADFM
SMP
Bit 7
GIE
IRP
(3)
—
—
—
—
ACKSTAT
INTEDG
PEIE
ADIE
Bit 6
CKE
RP1
(3)
—
—
—
—
PORTA Data Direction Register
TMR0IE
ACKDT
T0CS
Bit 5
RP0
D/A
2
(3)
—
—
—
—
C mode) Address Register
Write Buffer for the upper 5 bits of the Program Counter
ACKEN
T0SE
INTE
EEIE
Bit 4
TO
(3)
—
—
P
PCFG3
SSPIE
BCLIE
RCEN
RBIE
Bit 3
PSA
PD
—
S
TMR0IF
CCP1IE
PCFG2
Bit 2
PEN
PS2
R/W
—
—
Z
TMR2IE
PCFG1
RSEN
INTF
Bit 1
POR
PS1
DC
UA
—
© 2006 Microchip Technology Inc.
TMR1IE r0rr 0000 15, 94
PCFG0
RBIF
Bit 0
BOR
SEN
PS0
BF
(3)
C
0000 0000 21, 93
1111 1111 13, 94
0000 0000 20, 93
0001 1xxx 12, 93
xxxx xxxx 21, 93
--11 1111 29, 94
1111 1111 31, 94
1111 1111 33, 94
---0 0000 20, 93
0000 000x 14, 93
-r-0 0--r 17, 94
---- --qq 19, 94
0000 0000 54, 94
1111 1111 43, 94
0000 0000 58, 94
0000 0000 52, 94
xxxx xxxx 84, 94
0--- 0000
Value on:
POR,
BOR
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Details
80, 94
page:
on
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