PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 33

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Three pins of PORTB are multiplexed with the Low
Voltage Programming function; RB3/PGM, RB6/PGC
and RB7/PGD. The alternate functions of these pins
are described in the Special Features Section.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 4-3:
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
© 2006 Microchip Technology Inc.
Note 1:
RBPU
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
RB0/INT
RB3/PGM
2:
(2)
PORTB and the TRISB Register
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
Data Latch
TRIS Latch
D
D
CK
CK
Schmitt Trigger
Buffer
BLOCK DIAGRAM OF
RB3:RB0 PINS
Q
Q
Q
EN
D
TTL
Input
Buffer
DD
and V
V
RD Port
P
DD
Weak
Pull-up
I/O pin
SS
.
(1)
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 11.10.1.
FIGURE 4-4:
Note 1:
RBPU
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Set RBIF
RB7:RB6
In Serial Programming Mode
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
From other
RB7:RB4 pins
2:
(2)
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
TRIS Latch
Data Latch
D
D
CK
CK
BLOCK DIAGRAM OF
RB7:RB4 PINS
Q
Q
PIC16F872
Q
Q
Latch
EN
EN
D
DS30221C-page 31
D
TTL
Input
Buffer
DD
and V
V
P
DD
Weak
Pull-up
RD Port
I/O pin
Buffer
SS
Q1
.
Q3
ST
(1)