PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 65

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is IDLE, with both the S and P
bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
FIGURE 9-9:
9.2.6
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is IDLE with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the STOP condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
© 2006 Microchip Technology Inc.
SDA
SCL
MASTER MODE
MULTI-MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA In
SCL In
Bus Collision
Read
MSb
START bit, STOP bit,
Write Collision Detect
End of XMIT/RCV
START bit Detect,
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
SSPSR
Generate
2
2
C
C MASTER MODE)
LSb
Write
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (an SSP Interrupt will occur if
enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
PIC16F872
SSPADD<6:0>
SSPM3:SSPM0,
Baud
Rate
Generator
DS30221C-page 63