PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 55

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 9-2:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS: 14h)
bit 7
WCOL: Write Collision Detect bit
Master mode:
1 = A write to SSPBUF was attempted while the I
0 = No collision
Slave mode:
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
In SPI mode:
1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow.
0 = No overflow
In I
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
When enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I
0111 = I
1000 = I
1011 = I
1110 = I
1111 = I
1001, 1010, 1100, 1101 = reserved
Legend:
R = Readable bit
- n = Value at POR
SSPOV: Receive Overflow Indicator bit
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
WCOL
R/W-0
2
2
2
2
In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid over-
flows. In Master mode, the overflow bit is not set since each operation is initiated by writing to
the SSPBUF register. (Must be cleared in software.)
C mode:
Transmit mode. (Must be cleared in software.)
C mode:
C slave mode:
C master mode:
enabled
enabled
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C Firmware Controlled Master mode (slave idle)
C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts
C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts
SSPOV
R/W-0
W = Writable bit
’1’ = Bit is set
SSPEN
R/W-0
OSC
OSC
OSC
OSC
R/W-0
/4
/16
/64
/ (4 * (SSPADD+1)
CKP
2
C conditions were not valid
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
PIC16F872
x = Bit is unknown
SSPM1
R/W-0
DS30221C-page 53
SSPM0
R/W-0
bit 0