PIC16F1933-I/SP Microchip Technology Inc., PIC16F1933-I/SP Datasheet - Page 88

• Manufacturer Part Number: PIC16F1933-I/SP
• Description: 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1933-I/SP

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F193X/LF193X
6.3
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2 (Table 6-2).
TABLE 6-2:
6.3.1
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
V
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.3.2
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software
Registers” for more information.
6.4
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
“Watchdog Timer” for more information.
6.5
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.6
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration Word
2. See Section 3.4.2 “Overflow/Underflow Reset” for
more information.
DS41364D-page 88
DD
Note:
through an internal weak pull-up.
MCLRE
0
1
x
MCLR
Watchdog Timer (WDT) Reset
RESET Instruction
Stack Overflow/Underflow Reset
control.
MCLR ENABLED
A Reset does not drive the MCLR pin low.
MCLR DISABLED
MCLR CONFIGURATION
See
LVP
0
0
1
Section 12.6
Disabled
Enabled
Enabled
MCLR
“PORTE
Preliminary
6.7
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.8
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow V
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word 1.
6.9
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
2.
3.
The total time-out will vary based on oscillator configu-
ration and Power-up
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator start-
up timer will expire. Upon bringing MCLR high, the
device will begin execution immediately (see Figure 6-
4). This is useful for testing purposes or to synchronize
more than one device operating in parallel.
Power-up Timer runs to completion (if enabled).
Oscillator start-up timer runs to completion (if
required for oscillator source).
MCLR must be released (if enabled).
DD
Programming Mode Exit
Power-Up Timer
Start-up Sequence
to stabilize before allowing the device to start
 2009 Microchip Technology Inc.
Timer
configuration.
See