PIC16F1933-I/SP Microchip Technology Inc., PIC16F1933-I/SP Datasheet - Page 48

• Manufacturer Part Number: PIC16F1933-I/SP
• Description: 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1933-I/SP

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F193X/LF193X
TABLE 3-14:
DS41364D-page 48
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
Legend:
Note
Address
Bank 7
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1, 2)
(2)
1:
2:
3:
4:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
—
—
—
—
—
—
—
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are trans-
ferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices.
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
IOCBP7
IOCBN7
IOCBF7
Bit 7
GIE
—
—
—
Write Buffer for the upper 7 bits of the Program Counter
IOCBN6
IOCBP6
IOCBF6
Bit 6
PEIE
—
—
IOCBN5
TMR0IE
IOCBP5
IOCBF5
Bit 5
—
—
Preliminary
IOCBP4
IOCBN4
IOCBF4
INTE
Bit 4
TO
IOCBN3
IOCBP3
IOCBF3
IOCIE
Bit 3
PD
BSR<4:0>
IOCBN2
TMR0IF
IOCBP2
IOCBF2
Bit 2
Z
IOCBP1
IOCBN1
IOCBF1
INTF
Bit 1
DC
 2009 Microchip Technology Inc.
IOCBP0
IOCBN0
IOCBF0
IOCIF
Bit 0
C
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
POR, BOR
Value on:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Value on all
Resets
other
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—