PIC16F1933-I/SP Microchip Technology Inc., PIC16F1933-I/SP Datasheet - Page 248

• Manufacturer Part Number: PIC16F1933-I/SP
• Description: 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1933-I/SP

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F193X/LF193X
23.3
The Inter-Integrated Circuit Bus (I²C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A Slave device is
controlled through addressing.
The I
• Serial Clock (SCL)
• Serial Data (SDA)
Figure 23-11 shows the block diagram of the MSSP
module when operating in I
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 23-11 shows a typical connection between two
processors configured as master and slave devices.
The I
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
• Master Transmit mode
• Master Receive mode
• Slave Transmit mode
• Slave Receive mode
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a sin-
gle Read/Write bit, which determines whether the mas-
ter intends to transmit to or receive data from the slave
device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
DS41364D-page 248
(master is transmitting data to a slave)
(master is receiving data from a slave)
(slave is transmitting data to a master)
(slave is receiving data from the master)
2
2
C bus specifies two signal connections:
C bus can operate with one or more master
I
2
C
Mode Overview
2
C Mode.
Preliminary
FIGURE 23-11:
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmit-
ter that the slave device has received the transmitted
data and is ready to receive more.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.
If the master intends to write to the slave, then it repeat-
edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this exam-
ple, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is indi-
cated by a low-to-high transition of the SDA line while
the SCL line is held high.
In some cases, the master may want to maintain con-
trol of the bus and re-initiate another transmission. If
so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
The I
• Single message where a master writes data to a
• Single message where a master reads data from
• Combined message where a master initiates a
slave.
a slave.
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
Master
2
C bus specifies three message protocols;
SDA
SCL
V
V
I
SLAVE CONNECTION
2
DD
DD
 2009 Microchip Technology Inc.
C MASTER/
SCL
SDA
Slave