PIC16F1933-I/SP Microchip Technology Inc., PIC16F1933-I/SP Datasheet - Page 103

• Manufacturer Part Number: PIC16F1933-I/SP
• Description: 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1933-I/SP

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.5.5
The PIR1 register contains the interrupt flag bits, as
shown in Register 7-5.
REGISTER 7-5:
 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIF
R/W-0/0
PIR1 REGISTER
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
ADIF: A/D Converter Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
RCIF: USART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TXIF: USART Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
CCP1IF: CCP1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
R/W-0/0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R-0/0
RCIF
R-0/0
TXIF
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
SSPIF
PIC16F193X/LF193X
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
R/W-0/0
CCP1IF
software
R/W-0/0
TMR2IF
should
DS41364D-page 103
ensure
R/W-0/0
TMR1IF
bit 0
the