PIC16F1933-I/SP Microchip Technology Inc., PIC16F1933-I/SP Datasheet - Page 238
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16F1933-I/SP
Manufacturer Part Number
PIC16F1933-I/SP
Description
7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1933-ISS.pdf
(508 pages)
Specifications of PIC16F1933-I/SP
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1933-I/SP
Manufacturer:
NXP
Quantity:
1 000
Part Number:
PIC16F1933-I/SP
Manufacturer:
MICROCHI
Quantity:
20 000
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PIC16F193X/LF193X
The I
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 23-2 is a block diagram of the I
ule in Master mode. Figure 23-3 is a diagram of the I
interface module in Slave mode.
FIGURE 23-2:
DS41364D-page 238
2
C interface supports the following modes and
SDA
SCL
MSSP BLOCK DIAGRAM (I
SDA in
Bus Collision
SCL in
2
C interface mod-
Read
MSb
Generate (SSPCON2)
Address Match detect
Preliminary
Write collision detect
2
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock arbitration
C
Start bit detect,
Stop bit detect
Acknowledge
2
SSPBUF
C™ MASTER MODE)
SSPSR
LSb
Write
Clock
Shift
data bus
Internal
Set/Reset: S, P, SSPSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPCON2)
Set SSPIF, BCLIF
2009 Microchip Technology Inc.
[SSPM 3:0]
Baud rate
generator
(SSPADD)
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