PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 75

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

6.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Additional information on the Timer0 module is
available in the “PICmicro
Reference Manual” (DS33023).
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
Timer0
OPTION_REG register (see Register 2-2). Timer mode
is selected by clearing bit T0CS (OPTION_REG<5>).
In Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
FIGURE 6-1:
 2004 Microchip Technology Inc.
Note: T0CS, T0SE, PSA and PS2:PS0 are (OPTION_REG<5:0>).
RA4/T0CKI/C1OUT
WDT Enable bit
31.25 kHz
CLKO (= F
TIMER0 MODULE
Timer0 Operation
operation
pin
WDT Timer
OSC
Prescaler
16-bit
/4)
T0SE
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
is
®
controlled
Mid-Range MCU Family
0
1
0
1
T0CS
PSA
through
M
U
X
M
U
X
the
WDT Time-out
0
8-bit Prescaler
8-to-1 MUX
1
0
8
MUX
PSA
M
U
X
Counter mode is selected by setting bit, T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI/C1OUT.
determined by the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 6.3 “Using Timer0 With
an External Clock”.
The prescaler is mutually, exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 6.4
“Prescaler” details the operation of the prescaler.
6.2
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine before re-enabling this
interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the timer is shut-off during
Sleep.
Prescaler
1
Timer0 Interrupt
Cycles
Sync
PSA
2
PS2:PS0
The
PIC16F7X7
TMR0 Reg
incrementing
Data Bus
Set Flag bit TMR0IF
8
DS30498C-page 73
on Overflow
edge
is