PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 190

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
15.17.3
Two-Speed Start-up minimizes the latency between
oscillator start-up and code execution that may be
selected with the IESO (Internal/External Switchover)
bit in Configuration Word Register 2. This mode is
achieved by initially using the INTRC for code
execution until the primary oscillator is stable.
If this mode is enabled and any of the following condi-
tions exist, the system will begin execution with the
INTRC oscillator. This results in almost immediate
code execution with a minimum of delay.
• POR and after the Power-up Timer has expired (if
• or following a wake-up from Sleep
• or a Reset, when running from T1OSC or INTRC
If the primary oscillator is configured to be anything
other than XT, LP or HS, then Two-Speed Start-up is
disabled because the primary oscillator will not require
any time to become stable after POR or an exit from
Sleep.
If the IRCF bits of the OSCCON register are configured
to a non-zero value prior to entering Sleep mode, the
secondary system clock frequency will come from the
output of the INTOSC. The IOFS bit in the OSCCON
register will be clear until the INTOSC is stable. This
will allow the user to determine when the internal
oscillator can be used for time critical applications.
FIGURE 15-13:
DS30498C-page 188
System Clock
PWRTEN = 0)
(after a Reset, SCS<1:0> are always set to ‘00’).
Note:
Program
Counter
INTRC
OSC1
OSC2
OSTS
Sleep
TWO-SPEED CLOCK
START-UP MODE
Following any Reset, the IRCF bits are
zeroed and the frequency selection is
forced to 31.25 kHz. The user can modify
the IRCF bits to select a higher internal
oscillator frequency.
PC
CPU Start-up
TWO-SPEED START-UP
Q1
T
OST
0000h
Q4
Q1 Q2 Q3 Q4 Q1 Q2
Checking the state of the OSTS bit will confirm
whether the primary clock configuration is engaged. If
not, the OSTS bit will remain clear.
When the device is auto-configured in INTRC mode
following a POR or wake-up from Sleep, the rules for
entering other oscillator modes still apply, meaning the
SCS<1:0> bits in OSCCON can be modified before the
OST time-out has occurred. This would allow the
application to wake-up from Sleep, perform a few
instructions using the INTRC as the clock source and
go back to Sleep without waiting for the primary
oscillator to become stable.
15.17.3.1
1.
2.
3.
4.
5.
6.
7.
8.
The software may read the OSTS bit to determine
when the switchover takes place so that any software
timing edges can be adjusted.
0001h
Note:
Wake-up from Sleep, Reset or POR.
OSCON bits configured to run from INTRC
(31.25 kHz).
Instructions
(31.25 kHz).
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of INTRC.
OSTS is set.
System clock held low for eight falling edges of
new clock (LP, XT or HS).
System clock is switched to primary source (LP,
XT or HS).
Q3 Q4 Q1 Q2
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit to remain clear.
Two-Speed Start-up Sequence
0003h
begin
Q3 Q4
 2004 Microchip Technology Inc.
Q1 Q2 Q3 Q4
execution
0004h
by
0005h
INTRC