PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 161

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.6
Figure 12-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 12-4 shows the operation of the A/D converter
after
ACQT2:ACQT0 bits are set to ‘010’ and a 4 T
acquisition time is selected before the conversion
starts.
FIGURE 12-3:
FIGURE 12-4:
 2004 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
1
T
the
CY
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D Conversions
T
- T
ACQT
Acquisition
Automatic
2
GO/DONE
AD
Time
Conversion starts
T
Cycles
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
bit
4
2 T
Conversion starts
(Holding capacitor is disconnected)
AD
has
b8
1
3 T
been
AD
b7
b9
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
2
4 T
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
AD
set,
b6
b8
3
AD
AD
5 T
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
ADIF bit is set, holding capacitor is reconnected to analog input.
the
AD
AD
b5
4
b7
6 T
AD
b4
T
5
b6
AD
7 T
Cycles
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
AD
b3
Note:
b5
AD
6
8
wait is required before the next acquisition can be
T
conversion
AD
b2
b4
7
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
b1
b3
10
8
T
AD
b0
sample.
ACQ
b2
11
9
ACQ
PIC16F7X7
= 0)
= 4 T
10
b1
This
AD
DS30498C-page 159
b0
11
)
means
the