PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 22

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
TABLE 2-1:
DS30498C-page 20
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
Bank 2
Bank 3
(4)
(4)
(4)
(4)
(1,4)
(4)
(4)
(4)
(4)
(1,4)
(4)
(4)
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
INDF
TMR0
PCL
STATUS
FSR
WDTCON
PORTB
LVDCON
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
INDF
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
Shaded locations are unimplemented, read as ‘0’.
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
Name
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
Timer0 Module Register
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Reserved, maintain clear
Reserved, maintain clear
Reserved, maintain clear
RBPU
Bit 7
IRP
GIE
IRP
GIE
r
—
—
—
—
—
—
(6)
INTEDG
Bit 6
PEIE
PEIE
RP1
RP1
—
—
—
—
—
—
—
EEPROM Data Register High Byte
TMR0IE
TMR0IE
IRVST
T0CS
Bit 5
RP0
RP0
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
Write Buffer for the upper 5 bits of the Program Counter
WDTPS3
LVDEN
INT0IE
INT0IE
T0SE
Bit 4
TO
TO
—
—
EEPROM Address Register High Byte
WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000
LVDL3
RBIE
RBIE
Bit 3
PSA
PD
PD
—
TMR0IF
TMR0IF
LVDL2
Bit 2
PS2
—
Z
Z
INT0IF
INT0IF
LVDL1
Bit 1
PS1
DC
DC
—
 2004 Microchip Technology Inc.
LVDL0
RBIF
RBIF
Bit 0
PS0
RD
C
C
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx xxxx
--00 0101
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---- xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
---0 0000
0000 000x
1--- ---0
POR, BOR
Value on:
—
—
—
—
—
—
—
—
—
on page
30, 180
76, 180
29, 180
21, 180
30, 180
64, 180
23, 180
25, 180
32, 181
32, 181
32, 181
32, 181
30, 180
22, 180
29, 180
21, 180
30, 180
64, 181
23, 180
25, 180
32, 181
Details
187
176
—
—
—
—
—
—
—
—
—