PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 21

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-1:
 2004 Microchip Technology Inc.
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
Bank 1
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
OSCCON
OSCTUNE
SSPCON2
PR2
SSPADD
SSPSTAT
CCPR3L
CCPR3H
CCP3CON
TXSTA
SPBRG
ADCON2
CMCON
CVRCON
ADRESL
ADCON1
Shaded locations are unimplemented, read as ‘0’.
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
Name
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Timer2 Period Register
Synchronous Serial Port (I
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
Baud Rate Generator Register
Unimplemented
A/D Result Register Low Byte
PSPIE
C2OUT
CVREN
OSFIE
GCEN
RBPU
CSRC
ADFM
IBF
Bit 7
SMP
IRP
GIE
—
—
—
—
—
—
(5)
(3)
ACKSTAT
INTEDG
CVROE
C1OUT
ADCS2
OBF
IRCF2
CMIE
ADIE
Bit 6
PEIE
CKE
RP1
TX9
—
—
—
—
—
(5)
TMR0IE
IBOV
ACKDT
CCP3X
ACQT2
VCFG1
C2INV
LVDIE
IRCF1
CVRR
TUN5
TXEN
T0CS
RCIE
Bit 5
2
RP0
D/A
C™ mode) Address Register
—
—
(5)
PSPMODE
Write Buffer for the upper 5 bits of the Program Counter
ACKEN
CCP3Y
ACQT1
VCFG0
INT0IE
IRCF0
C1INV
SYNC
T0SE
TUN4
Bit 4
TXIE
TO
—
—
—
P
(5)
CCP3M3
OSTS
ACQT0
PCFG3
SSPIE
BCLIE
RCEN
TUN3
CVR3
RBIE
Bit 3
PSA
—
CIS
PD
—
—
S
(8)
(7)
PORTE Data Direction bits
SBOREN
CCP3M2
TMR0IF
CCP1IE
PCFG2
BRGH
TUN2
CVR2
IOFS
Bit 2
PEN
CM2
PS2
R/W
—
—
Z
CCP3M1 CCP3M0 --00 0000
TMR2IE
CCP3IE
PCFG1
INT0IF
TUN1
RSEN
TRMT
CVR1
SCS1
Bit 1
POR
CM1
PS1
DC
UA
—
PIC16F7X7
TMR1IE 0000 0000
CCP2IE
PCFG0
CVR0
SCS0
TUN0
TX9D
RBIF
Bit 0
BOR
SEN
CM0
PS0
BF
—
C
DS30498C-page 19
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
1111 1111
1111 1111
0000 1111
---0 0000
0000 000x
000- 0-00
---- -1qq
-000 1000
--00 0000
0000 0000
1111 1111
0000 0000 101, 181
0000 0000 101, 181
xxxx xxxx
xxxx xxxx
0000 -010 145, 181
0000 0000 145, 181
--00 0---
0000 0111
000- 0000
xxxx xxxx
0000 0000 153, 181
POR, BOR
Value on:
—
on page
30, 180
22, 180
29, 180
21, 180
30, 180
55, 181
64, 181
66, 181
67, 181
69, 181
23, 180
25, 180
24, 181
26, 181
28, 181
38, 181
36, 181
86, 181
55, 161
55, 167
Details
105
154
180
92
92
92
—