PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 351

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 27-2:
REGISTER 27-3:
 2010 Microchip Technology Inc.
bit 4
bit 3-2
bit 1-0
bit 23
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 23-16
bit 15
bit 14
bit 13
bit 12
Note 1:
WPEND
WPFP7
R/PO-1
R/PO-1
U-0
—
2:
3:
Unimplemented in 64-pin devices, maintain at ‘1’.
Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-1.
Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page,
the Configuration Word’s page is protected.
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
Reserved: Always maintain as ‘1’
POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
Unimplemented: Read as ‘1’
WPEND: Segment Write Protection End Page Select bit
1 = Protected code segment upper boundary is at the last page of program memory; the lower
0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper
WPCFG: Configuration Word Code Page Write Protection Select bit
1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected
0 = Last page and Flash Configuration Words are write-protected, provided WPDIS = ‘0’
WPDIS: Segment Write Protection Disable bit
1 = Segmented code protection is disabled
0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and
ALTPMP: Alternate EPMP Pin Mapping bit
1 = EPMP pins are in default location mode
0 = EPMP pins are in alternate location mode
WPCFG
WPFP6
R/PO-1
R/PO-1
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
completed
boundary is the code page specified by WPFP<7:0>
boundary is the code page specified by WPFP<7:0>
WPFPx Configuration bits
U-0
—
CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
CW3: FLASH CONFIGURATION WORD 3
PO = Program-Once bit
W = Writable bit
‘1’ = Bit is set
WPFP5
R/PO-1
R/PO-1
WPDIS
U-0
—
ALTPMP
PIC24FJ256DA210 FAMILY
WPFP4
R/PO-1
R/PO-1
U-0
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WUTSEL1
R/PO-1
R/PO-1
WPFP3
U-0
—
WUTSEL0
WPFP2
R/PO-1
R/PO-1
U-0
—
x = Bit is unknown
SOSCSEL1
WPFP1
R/PO-1
R/PO-1
U-0
—
DS39969B-page 351
SOSCSEL0
WPFP0
R/PO-1
R/PO-1
U-0
—
bit 16
bit 8
bit 0
(3)