PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 297

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

21.0
FIGURE 21-1:
FIGURE 21-2:
 2010 Microchip Technology Inc.
Note:
Note 1: n = PLEN<4:1> + 1.
Shift Buffer
32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
CRCDATH
Data
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Section
Cyclic
(DS39729). The information in this data
sheet supersedes the information in the
FRM.
(4x32, 8x16 or 16x8)
CRC Shift Engine
Variable FIFO
Shift Buffer
Redundancy
41.
Family
CRC BLOCK DIAGRAM
CRC SHIFT ENGINE DETAIL
X0
CRCDATL
“32-Bit
Reference
Bit 0
Check
Shifter Clock
Programmable
2 * F
LENDIAN
CY
1
0
Manual”,
CRCWDATH
(CRC)”
PIC24FJ256DA210 FAMILY
X1
Read/ W rite Bus
CRCWDATH
CRC Shift Engine
Bit 1
The 32-bit programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable interrupt output
• Data FIFO
Figure 21-1 displays a simplified block diagram of the
CRC generator. A simple version of the CRC shift
engine is displayed in Figure 21-2.
up to 32 bits
FIFO Empty
Event
CRCWDATL
CRCWDATL
Xn
(1)
Complete
Event
Shift
CRCISEL
DS39969B-page 297
Bit n
1
0
(1)
Interrupt
CRC