PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 24

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC24FJ256DA210 FAMILY
TABLE 1-3:
DS39969B-page 24
CN81
CN82
CN83
CN84
CTEDG1
CTEDG2
CTPLS
CV
D+
D-
DMH
DMLN
DPH
DPLN
ENVREG
GCLK
GD0
GD1
GD2
GD3
GD4
GD5
GD6
GD7
GD8
GD9
GD10
GD11
GD12
GD13
GD14
GD15
GEN
GPWR
HSYNC
INT0
MCLR
OSCI
OSCO
Legend:
Note 1:
Function
REF
2:
3:
4:
TTL = TTL input buffer
ANA = Analog level input/output
The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’.
The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
The alternate V
TQFP/QFN
64-Pin
37
36
23
37
36
52
60
62
63
31
32
44
45
49
58
59
51
46
39
40
—
—
28
27
29
46
42
50
43
57
61
43
53
64
2
3
6
8
7
PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
REF
100-Pin
TQFP
pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.
95
57
56
42
41
43
34
57
56
72
68
77
69
86
39
52
21
22
23
76
53
69
77
32
33
47
48
91
27
97
72
13
63
64
1
1
6
8
7
121-Pin
BGA
H10
H10
A10
E10
K11
A11
E10
A10
J11
J11
J10
F11
C4
B2
K7
D9
E9
B2
D1
E2
H2
E4
K4
K9
C5
A3
D9
L7
L5
L6
L4
L9
F1
F9
J7
J7
J1
J2
J3
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Buffer
Input
ANA
ANA
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ST = Schmitt Trigger input buffer
I
2
C™ = I
Interrupt-on-Change Inputs.
CTMU External Edge Input 1.
CTMU External Edge Input 2.
CTMU Pulse Output.
Comparator Voltage Reference Output.
USB Differential Plus Line (internal transceiver).
USB Differential Minus Line (internal transceiver).
D- External Pull-up Control Output.
D- External Pull-down Control Output.
D+ External Pull-up Control Output.
D+ External Pull-down Control Output.
Voltage Regulator Enable.
Graphics Display Pixel Clock.
Graphics Controller Data Output.
Graphics Display Enable Output.
Graphics Display Power System Enable.
Graphics Display Horizontal Sync Pulse.
External Interrupt Input.
Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
Main Oscillator Input Connection.
Main Oscillator Output Connection.
2
C/SMBus input buffer
Description
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