PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 139

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 7-42:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-8
bit 7
bit 6-0
R-0, HSC
CPUIRQ
U-0
—
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
0 = No interrupt request is unacknowledged
Unimplemented: Read as ‘0’
VHOLD: Vector Number Capture Configuration bit
1 = The VECNUM bits contain the value of the highest priority pending interrupt
0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
Unimplemented: Read as ‘0’
VECNUM<5:0>: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits
VHOLD = 1: The VECNUM bits indicate the vector number (from 0 to 118) of the last interrupt to occur
VHOLD = 0: The VECNUM bits indicate the vector number (from 0 to 118) of the interrupt request
VECNUM6
R-0, HSC
when the CPU priority is higher than the interrupt priority
has occurred with higher priority than the CPU, even if other interrupts are pending)
U-0
—
INTTREG: INTERRUPT CONTROLLER TEST REGISTER
currently being handled
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
VECNUM5
R-0, HSC
VHOLD
R/W-0
VECNUM4
R-0, HSC
PIC24FJ256DA210 FAMILY
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
VECNUM3
R-0, HSC
R-0, HSC
ILR3
VECNUM2
R-0, HSC
R-0, HSC
ILR2
x = Bit is unknown
VECNUM1
R-0, HSC
R-0, HSC
ILR1
DS39969B-page 139
VECNUM0
R-0, HSC
R-0, HSC
ILR0
bit 8
bit 0