DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 67

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.33 Receive Descriptor Pointer 3 Register
This register points to the Receive Descriptor for Priority Queue 3 (highest priority).
4.2.34 VLAN/IP Receive Control Register
This register allows enabling of the various VLAN tag handling features and IP Checksum offload features.
31-3
31-8
2-0
bit
bit
7
6
5
4
3
2
1
0
RUDPE
RXDP3
RTCPE
VTREN
VTDEN
DUTF
DVTF
RIPE
IPEN
tag
tag
Offset: 00B8h
Offset: 00BCh
Receive
Descriptor Pointer
3
Reject UDP
Checksum Errors
Reject TCP
Checksum Errors
Reject IP
Checksum Errors
IP Checksum
Enable
Discard Untagged
Frames
Discard VLAN
Tagged Frames
VLAN Tag
Removal Enable
VLAN Tag
Detection Enable
(Continued)
Tag: RXDP3
Tag: VRCR
description
description
The current value of the receive descriptor pointer for Priority Queue 3. Packets will be
stored in Priority Queue 3 based on the number of priority queues enabled and the
priority field in the VLAN tag. When the receive state machine is idle, software must set
RXDP3 to the address of an available receive descriptor, and then enable the queue by
writing to the RXE bit in the CR with the RXPRI[3] bit set. While the receive state machine
is active, RXDP3 will follow the state machine as it advances through a linked list of
available descriptors. If the link field of the current receive descriptor is NULL (signifying
the end of the list), RXDP3 will not advance, but will remain on the current descriptor. Any
subsequent writes to the RXE bit of the CR register will cause the receive state machine
to reread the link field of the current descriptor to check for new descriptors that may have
been appended to the end of the list. Software should not write to this register unless the
receive state machine is idle. Receive descriptors must be aligned on 64-bit boundaries
(A2-A0 must be zero).
unused
unused
When set to 1, all packets with UDP headers that have errors in the UDP checksum field
will be rejected. If IPEN is 0, this bit will be ignored.
When set to 1, all packets with TCP headers that have errors in the TCP checksum field
will be rejected. If IPEN is 0, this bit will be ignored.
When set to 1, all packets with IP headers that have errors in the IP checksum field will be
rejected. If IPEN is 0, this bit will be ignored.
When set to a 1, the receiver will detect IP , TCP, and UDP headers, and validate the
checksum fields.
Receiver will discard any frames without a1 VLAN tag.
Receiver will discard any frames with a VLAN tag.
Enables stripping of the VLAN tag upon detection. If VTDEN is not set, then this bit will
have no effect.
Enable detection of VLAN packets based on VLAN type field as configured in the VLAN
Data Register. VLAN status, including user_priority, CFI and VID fields, will be posted in
the EXTSTS field of the receive packet descriptor.
Access: Read Write
Access: Read Write
Size: 32 bits
Size: 32 bits
67
usage
usage
Hard Reset: 00000000h
Hard Reset: 00000000h
Soft Reset: 00000000h
Soft Reset: 00000000h
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