DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 34

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.1.3 Configuration Revision ID Register
This register stores the silicon revision number, revision number of software interface specification and lets the
configuration software know that it is an Ethernet controller in the class of network controllers.
4.1.4 Configuration Latency Timer Register
This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size.
DP83820 Bus Master Operations:
Based on cache line size, the DP83820 will use the following PCI commands for bus mastered transfers:
31-24
23-16
29-16
15-8
15-8
7-0
7-0
bit
bit
31
30
0110 - Mem Read
1110 - Mem Read Line
1100 - Mem Read Multiple
0111 - Mem Write
1111 - Mem Write Invalidate Writes that exactly overwrite 1 or more cachelines
BISTCAP
BASECL
PROGIF
BISTEN
SUBCL
REVID
CLS
LAT
tag
tag
Offset: 08h
Offset: 0Ch
(Continued)
Tag: CFGRID
Tag: CFGLAT
Base Class
Sub Class
Programming IF
Silicon Revision
BIST Capable
BIST Enable
Reserved
Latency Timer
Cache Line Size
description
description
Single dword read transfers
Read More than 1 dword but not across a cacheline boundary
Read transfers that cross a cacheline boundary
Writes that do not exactly overwrite 1 or more cachelines
Access: Read Only
Access: Read Write
Returns 02h which specifies a network controller.
Returns 00h which specifies an Ethernet controller.
Returns 00h which specifies the first release of the DP83820.
Returns 00h which specifies the silicon revision.
Reads will always return 0.
Reads will return a 0, writes are ignored.
Reads will return a 0, writes are ignored.
Set by software to the number of PCI clocks that DP83820 may hold the
PCI bus.
Set to the value of the system cache line size in dwords. Acceptable values
are powers of 2 less than or equal to 128. All other values will be
recognized as 0.
Size: 32 bits
Size: 32 bits
34
usage
usage
Hard Reset: 02000000h
Hard Reset: 00000000h
Soft Reset: Unchanged
Soft Reset: Unchanged
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