DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 33

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.1.2 Configuration Command and Status Register
The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. The lower 16-bits (15-0) are
devoted to command and are used to configure and control the device.
31-16
26-25
19-16
15-10
15-0
bit
31
30
29
28
27
24
23
22
21
20
9
8
7
6
5
4
3
2
1
0
M66_CAP
SERREN
PERRSP
DPERR
SSERR
RMABT
NCPEN
MWIEN
FBBEN
RTABT
STABT
DSTIM
IOSEN
BMEN
MSEN
CMD
DPD
STS
FBB
tag
Offset: 04h
(Continued)
Tag: CFGCS
Status
Detected Parity Error
Signaled SERR
Received Master Abort
Received Target Abort
Sent Target Abort
DEVSELN Timing
Data Parity Detected
Fast Back-to-Back Capable
66MHz Capable
New Capabilities Enable
Unused
Command
Unused
Fast Back-to-Back Enable
SERRN Enable
Parity Error Response
Unused
Memory Write and Invalidate
Enable
Unused
Bus Master Enable
Memory Space Access
IO Space Access
Unused
description
Access: Read Write
Device Status Bits. A status bit is reset whenever the register is written, and
the corresponding bit location is a 1.
Refer to the description in the PCI V2.2 specification.
Refer to the description in the PCI V2.2 specification.
Refer to the description in the PCI V2.2 specification.
Refer to the description in the PCI V2.2 specification.
Refer to the description in the PCI V2.2 specification.
This field will always be set to 01 indicating that DP83820 supports
“medium” DEVSELN timing.
Refer to the description in the PCI V2.2 specification.
DP83820 will set this bit to 1.
unused (reads return 0)
This field indicates the device is 66MHz capable. It will be loaded from
EEPROM.
When set, this bit indicates that the Capabilities Pointer contains a valid
value and new capabilities such as power management are supported.
When clear, new capabilities (CAPPTR, PMCAP , PMCS) are disabled. The
value in this register will either be loaded from the EEPROM or, if the
EEPROM is disabled, from a strap option at reset.
Unused (reads return 0)
Device Command bits (see below).
Unused (reads return 0)
Set to 1 by the PCI BIOS to enable the DP83820 to do Fast Back-to-Back
transfers (FBB transfers as a master is not implemented in the current
revision).
When set, DP83820 will generate SERRN when an address parity error is
detected.
Unused (reads return 0)
When set, DP83820 will assert PERRN on the detection of a data parity
error when acting as the target, and will sample PERRN when acting as the
initiator. When reset, data parity errors are ignored. The action taken is
specified by CFG: PESEL.
Unused (reads return 0)
When set, DP83820 may use the Memory Write and Invalidate command
for qualifying transfers. If 0, Memory Write will always be used instead of
MWI. The DP83820 further qualifies enabling the MWI command using the
MWI_DIS bit in the CFG operational register.
Unused (reads return 0)
When set, DP83820 is allowed to act as a PCI bus master. When reset,
DP83820 is prohibited from acting as a PCI bus master.
When set, DP83820 responds to memory space accesses. When reset,
DP83820 ignores memory space accesses.
When set, DP83820 responds to IO space accesses. When reset,
DP83820 ignores IO space accesses.
Size: 32 bits
33
usage
Hard Reset: 02900000h
Soft Reset: Unchanged
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