DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 42

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXTSTS_EN Extended Status Enable
PCI64_DET
DATA64_EN 64-bit Data Enable
BROM_DIS
M64ADDR
MRM_DIS
PHY_RST
T64ADDR
MWI_DIS
PHY_DIS
REQALG
EXT_125
PESEL
POW
BEM
EXD
SB
(Continued)
Memory Read Multiple
Disable
Memory Write and Invalidate
Disable
Target 64-bit Addressing
Enable
PCI 64-bit Bus Detected
Master 64-bit Addressing
Enable
Reset Phy
Disable Phy
PCI Bus Request Algorithm
Single Back-off
Program Out of Window
Timer
Excessive Deferral Abort
Parity Error Detection Action
Disable Boot ROM interface
External 125MHz reference
Select
Big Endian Mode
This bit can be used to prevent the DP83820 from using the Memory Read
Multiple and Memory Read Line commands. This bit is loaded from
EEPROM at power-up. R/W
This bit can be used to prevent the DP83820 from using the MWI
command. This allows additional control for driver software which may not
have access to the MWIEN bit in Configuration space. This bit is loaded
from EEPROM at power-up. R/W
This read-only bit indicates the device will accept 64-bit addressing as a
target. This bit is loaded from EEPROM at power-up. RO
This status bit indicates the PCI bus was detected to be 64-bit at reset time.
RO
Software can use this bit to enable 64-bit data transfers by the Transmit and
Receive DMA engines. If 0, all bus master transfers will be 32-bit. This bit is
loaded from EEPROM at power-up. This bit should be cleared by software if
the PCI bus was not detected as 64-bit capable (PCI_64_DET = 0). R/W
Software can set this bit to enable the DMA controllers to use 64-bit
addressing. When set, the link and bufptr fields in the Descriptors are
assumed to be 64-bit fields. This bit does not affect the device operation as
a target. This bit is loaded from EEPROM at power-up. R/W
Asserts reset to phy using the PHYRST_N pin. R/W
Setting this bit can be used to disable an external phy by deasserting the
RXEN pin. This can be used to cause a phy to tri-state its RX MII/GMII pins.
R/W
When set, the Extended Status field is enabled for Transmit and Receive
Descriptors. This field contains data for supporting the VLAN and IP
Checksum processing features. R/W
Selects mode for making requests for the PCI bus. When set to 0 (default),
DP83820 will use an aggressive Request scheme. When set to a 1
DP83820 will use a more conservative scheme. R/W
Setting this bit to 1, forces the transmitter back-off state machine to always
back-off for a single 802.3 interframe gap time, instead of following the
802.3 random back-off algorithm. A 0 (default) allows normal transmitter
back-off operation. R/W
This bit controls when the Out of Window collision timer begins counting its
512 bit slot time. A 0 causes the timer to start after the SFD is received. A 1
causes the timer to start after the first bit of the preamble is received. R/W
Setting this bit to 1 will cause the transmitter to abort transmission on an
excessive deferral. R/W
This bit controls the assertion of SERR when a data parity error is detected
while the DP83820 is acting as the bus master. When set, parity errors will
not result in the assertion of SERR. When reset, parity errors will result in
the assertion of SERR, indicating a system error. This bit should be set to a
1 by software if the driver can handle recovery from and reporting of data
parity errors. R/W
When set to 1, this bit inhibits the operation of the Boot ROM interface logic.
R/W
When set to a 1, the 125MHz transmit clock for 1000 Mb/s mode is sourced
from the REF125 pin. When set to a 0, the clock is sourced by the internal
clock generator. This bit is loaded from EEPROM at power-up. R/W
When set, DP83820 will perform bus-mastered data transfers in “big
endian” mode. Note that access to register space is unaffected by the
setting of this bit. R/W
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