DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 49

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.11 Transmit Descriptor Pointer High Dword Register
This register points to the upper 32-bits of the current Transmit Descriptor for 64-bit addressing. If Transmit Priority
Queueing is enabled, this becomes the Descriptor pointer for all priority queues.
4.2.12 Transmit Configuration Register
This register defines the Transmit Configuration for DP83820. It controls such functions as Loopback, Heartbeat, Auto
Transmit Padding, programmable Interframe Gap, Fill & Drain Thresholds, and maximum DMA burst size.
27-24
31-0
bit
bit
31
30
29
28
23
ECRETRY
TXDP_HI
MLB
ATP
CSI
HBI
tag
tag
Offset: 0024h
Offset: 0028h
(Continued)
Tag: TXDP_HI
Tag: TXCFG
Transmit Descriptor Pointer
High Dword
Carrier Sense Ignore
HeartBeat Ignore
MAC Loopback
Automatic Transmit Padding
Excessive Collision Retry
Enable
description
description
Access: Read Write
Access: Read Write
If 64-bit addressing is enabled, this will be used as the upper 32-bits of the
current transmit descriptor pointer.
Setting this bit to 1 causes the transmitter to ignore carrier sense activity,
which inhibits reporting of CRS status to the transmit status register, and
inhibits logging of TXCSErrors in the MIB counter block. When this bit is 0
(default), the transmitter will monitor the CRS signal during transmission
and reflect valid status in the transmit status register and MIB counter
block. This bit must be set to enable full-duplex operation.
Setting this bit to 1 causes the transmitter to ignore the heartbeat (CD)
pulse which follows the packet transmission and inhibits logging of
TXSQEErrors in the MIB counter block. When this bit is set to 0 (default),
the transmitter will monitor the heartbeat pulse and log TXSQEErrors to the
MIB counter block. This bit must be set to enable full-duplex operation
Setting this bit to a 1 places the DP83820 MAC into a loopback state which
routes all transmit traffic to the receiver, and disables the transmit and
receive interfaces of the MII. A 0 in this bit allows normal MAC operation.
The transmitter and receiver must be disabled before enabling the loopback
mode. (Packets received during MLB mode will reflect loopback status in
the receive descriptor’s
Setting this bit to 1 causes the MAC to automatically pad small (runt)
transmit packets to the Ethernet minimum size of 64 bytes. This allows
driver software to transfer only actual packet data. Setting this bit to 0
disables the automatic padding function, forcing software to control runt
padding.
unused
This bit enables automatic retries of excessive collisions. If set, the
transmitter will retry the packet up to 4 excessive collision counts, for a total
of 64 attempts. If the packet still does not complete successfully, then the
transmission will be aborted after the 64th attempt. If this bit is not set, then
the transmission will be aborted after the 16th attempt. Note that setting
this bit will change how collisions are reported in the status field of the
transmit descriptor.
Size: 32 bits
Size: 32 bits
49
cmdsts.LBP
usage
usage
Hard Reset: 00000000h
Hard Reset: 00000120
Soft Reset: 00000000h
Soft Reset: 00000120
field.)
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