ISP1583BSGA ST-Ericsson Inc, ISP1583BSGA Datasheet - Page 50

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ISP1583BSGA

Manufacturer Part Number
ISP1583BSGA
Description
IC USB CTRL HI-SPEED 64HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1583BSGA

Controller Type
USB Peripheral Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISP1583BS-S
ISP1583BS-S
NXP Semiconductors
ISP1583_7
Product data sheet
9.4.2 DMA Transfer Counter register (address: 34h)
Table 53.
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates
the remaining number of bytes left for transfer. The bit allocation is given in
For IN endpoint — Because there is a FIFO in the ISP1583 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and
the maximum delay time for data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint — Data will not be cleared from the endpoint buffer, until all the data is
read from the DMA FIFO.
Code
11h
12h
13h
14h to 20h
21h
22h
23h
24h
25h
26h
27h
28h
29h to FFh
DMA commands
Name
Reset DMA
MDMA stop
GDMA stop
-
Read Task File
register 1F1h
Read Task File
register 1F2h
Read Task File
register 1F3h
Read Task File
register 1F4h
Read Task File
register 1F5h
Read Task File
register 1F6h
Read Task File
register 3F6h
Read Task File
register 3F7h
-
Rev. 07 — 22 September 2008
…continued
Description
Reset DMA: Initializes the DMA core to its power-on reset state.
Remark: When the DMA core is reset during the Reset DMA
command, the DREQ, DACK, DIOW and DIOR handshake pins
will temporarily be asserted. This can confuse the external DMA
controller. To prevent this, start the external DMA controller only
after the DMA reset.
MDMA stop: This command immediately stops the MDMA data
transfer. This is applicable for commands 06h and 07h only.
GDMA stop: This command stops the GDMA data transfer. Any
data in the OUT endpoint that is not transferred by the DMA will
remain in the buffer. The FIFO data for the IN endpoint will be
written to the endpoint buffer. An interrupt bit will be set to
indicate the completion of the DMA Stop command.
Remark: For the DMA OUT transfer, if the DMA Burst Counter
register is programmed to some value, for example 512 bytes,
and if a GDMA Stop command is issued in the middle of a
transfer, the transfer will continue until the end of the burst size
(512 bytes). Issuing a GDMA Stop command does not allow the
ISP1583 to stop in the middle of the burst. It can only be stopped
in between bursts.
reserved
Read Task File register 1F1h: When reading is completed, an
interrupt is generated.
Read Task File register 1F2h: When reading is completed, an
interrupt is generated.
Read Task File register 1F3h: When reading is completed, an
interrupt is generated.
Read Task File register 1F4h: When reading is completed, an
interrupt is generated.
Read Task File register 1F5h: When reading is completed, an
interrupt is generated.
Read Task File register 1F6h: When reading is completed, an
interrupt is generated.
Read Task File register 3F6h: When reading is completed, an
interrupt is generated.
Read Task File register 3F7h: When reading is completed, an
interrupt is generated.
reserved
Hi-Speed USB peripheral controller
© NXP B.V. 2008. All rights reserved.
ISP1583
Table
54.
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