ISP1583BSGA ST-Ericsson Inc, ISP1583BSGA Datasheet - Page 62

• Manufacturer Part Number: ISP1583BSGA
• Description: IC USB CTRL HI-SPEED 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSGA

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1583BS-S; ISP1583BS-S

NXP Semiconductors
Table 84.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Chip ID register: bit allocation
9.5.2 Chip ID register (address: 70h)
23
15
R
R
R
0
0
1
1
7
0
0
Table 83.
This read-only register contains the chip identification and hardware version numbers.
The firmware must check this information to determine functions and features supported.
The register contains 3 bytes, and the bit allocation is shown in
Bit
10
9
8
7
6
5
4
3
2
1
0
22
14
R
R
R
0
0
0
0
6
0
0
Interrupt register: bit description
Symbol
EP0RX
-
EP0SETUP
VBUS
DMA
HS_STAT
RESUME
SUSP
PSOF
SOF
BRESET
21
13
R
R
R
0
0
0
0
5
1
1
Rev. 07 — 22 September 2008
Description
logic 1 indicates the endpoint 0 data RX buffer as interrupt source
reserved
logic 1 indicates that a SETUP token was received on endpoint 0
logic 1 indicates a transition from LOW to HIGH on V
DMA status: Logic 1 indicates a change in the DMA Interrupt Reason
register.
High-Speed Status: Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set, when the system
goes into full-speed suspend.
Resume Status: Logic 1 indicates that a status change from suspend
to resume (active) was detected.
Suspend Status: Logic 1 indicates that a status change from active to
suspend was detected on the bus.
Pseudo SOF Interrupt: Logic 1 indicates that a pseudo SOF or SOF
was received. Pseudo SOF is an internally generated clock signal
(full-speed: 1 ms period, high-speed: 125 s period) that is not
synchronized to the USB bus SOF or SOF.
SOF Interrupt: Logic 1 indicates that a SOF or SOF was received.
Bus Reset: Logic 1 indicates that a USB bus reset was detected. When
bit OTG in the OTG register is set, BRESET will not be set, instead, this
interrupt bit will report SE0 on DP and DM for 2 ms.
20
12
R
R
R
1
1
0
0
4
1
1
VERSION[7:0]
CHIPID[15:8]
CHIPID[7:0]
…continued
19
11
R
R
R
0
0
0
0
3
0
0
Hi-Speed USB peripheral controller
18
10
R
R
R
1
1
0
0
2
0
0
Table
17
84.
R
R
R
0
0
9
1
1
1
0
0
© NXP B.V. 2008. All rights reserved.
BUS
ISP1583
16
R
R
R
1
1
8
0
0
0
0
0
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