ISP1583BSGA ST-Ericsson Inc, ISP1583BSGA Datasheet - Page 96

• Manufacturer Part Number: ISP1583BSGA
• Description: IC USB CTRL HI-SPEED 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSGA

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1583BS-S; ISP1583BS-S

NXP Semiconductors
23. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Operation truth table for clock off
Table 11. Operation truth table for back voltage
Table 12. Operation truth table for OTG . . . . . . . . . . . . .25
Table 13. Operation truth table for SoftConnect . . . . . . .26
Table 14. Operation truth table for clock off
Table 15. Operation truth table for back voltage
Table 16. Operation truth table for OTG . . . . . . . . . . . . .27
Table 17. Operation truth table for SoftConnect . . . . . . .27
Table 18. Operation truth table for clock off during
Table 19. Operation truth table for back voltage
Table 20. Operation truth table for OTG . . . . . . . . . . . . .28
Table 21. Register overview . . . . . . . . . . . . . . . . . . . . . .29
Table 22. Address register: bit allocation . . . . . . . . . . . .31
Table 23. Address register: bit description . . . . . . . . . . .31
Table 24. Mode register: bit allocation . . . . . . . . . . . . . . .32
Table 25. Mode register: bit description . . . . . . . . . . . . .32
Table 26. Status of the chip . . . . . . . . . . . . . . . . . . . . . . .33
Table 27. Interrupt Configuration register: bit allocation .34
Table 28. Interrupt Configuration register: bit description 34
Table 29. Debug mode settings . . . . . . . . . . . . . . . . . . . .34
Table 30. OTG register: bit allocation . . . . . . . . . . . . . . .34
Table 31. OTG register: bit description . . . . . . . . . . . . . .35
Table 32. Interrupt Enable register: bit allocation . . . . . .37
Table 33. Interrupt Enable register: bit description . . . . .37
Table 34. Endpoint Index register: bit allocation . . . . . . .38
Table 35. Endpoint Index register: bit description . . . . . .39
Table 36. Addressing of endpoint buffers . . . . . . . . . . . .39
Table 37. Control Function register: bit allocation . . . . . .39
Table 38. Control Function register: bit description . . . . .40
Table 39. Data Port register: bit allocation . . . . . . . . . . .41
Table 40. Data Port register: bit description . . . . . . . . . .41
Table 41. Buffer Length register: bit allocation . . . . . . . .42
Table 42. Buffer Length register: bit description . . . . . . .42
ISP1583_7
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Endpoint access and programmability . . . . . . .13
Bus configuration modes . . . . . . . . . . . . . . . . .17
ISP1583 pin status . . . . . . . . . . . . . . . . . . . . . .17
ISP1583 output pin status . . . . . . . . . . . . . . . .17
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .23
Operation truth table for SoftConnect . . . . . . .25
during suspend . . . . . . . . . . . . . . . . . . . . . . . .25
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
during suspend . . . . . . . . . . . . . . . . . . . . . . . .26
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Rev. 07 — 22 September 2008
Table 43. Buffer Status register: bit allocation . . . . . . . . 43
Table 44. Buffer Status register: bit description . . . . . . . 43
Table 45. Endpoint MaxPacketSize register:
Table 46. Endpoint MaxPacketSize register:
Table 47. Endpoint Type register: bit allocation . . . . . . . 44
Table 48. Endpoint Type register: bit description . . . . . . 45
Table 49. Control bits for Generic DMA transfers . . . . . . 46
Table 50. Control bits for IDE-specified DMA transfers . . 47
Table 51. DMA Command register: bit allocation . . . . . . 47
Table 52. DMA Command register: bit description . . . . . 48
Table 53. DMA commands . . . . . . . . . . . . . . . . . . . . . . . 48
Table 54. DMA Transfer Counter register: bit allocation . 50
Table 55. DMA Transfer Counter register: bit description 50
Table 56. DMA Configuration register: bit allocation . . . . 50
Table 57. DMA Configuration register: bit description . . . 51
Table 58. DMA Hardware register: bit allocation . . . . . . . 52
Table 59. DMA Hardware register: bit description . . . . . 52
Table 60. Task File register functions . . . . . . . . . . . . . . . 53
Table 61. ATAPI peripheral register addressing . . . . . . . 53
Table 62. Task File 1F0 register (address: 40h):
Table 63. Task File 1F1 register (address: 48h):
Table 64. Task File 1F2 register (address: 49h):
Table 65. Task File 1F3 register (address: 4Ah):
Table 66. Task File 1F4 register (address: 4Bh):
Table 67. Task File 1F5 register (address: 4Ch):
Table 68. Task File 1F6 register (address: 4Dh):
Table 69. Task File 1F7 register (address: 44h):
Table 70. Task File 3F6 register (address: 4Eh):
Table 71. Task File 3F7 register (address: 4Fh):
Table 72. DMA Interrupt Reason register: bit allocation . 56
Table 73. DMA Interrupt Reason register: bit description 56
Table 74. Internal EOT-functional relation with
Table 75. DMA Interrupt Enable register: bit allocation . . 57
Table 76. DMA Endpoint register: bit allocation . . . . . . . 58
Table 77. DMA Endpoint register: bit description . . . . . . 58
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . . 57
Hi-Speed USB peripheral controller
© NXP B.V. 2008. All rights reserved.
ISP1583
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