ISP1583BSGA ST-Ericsson Inc, ISP1583BSGA Datasheet - Page 41

• Manufacturer Part Number: ISP1583BSGA
• Description: IC USB CTRL HI-SPEED 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSGA

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1583BS-S; ISP1583BS-S

NXP Semiconductors
ISP1583_7
Product data sheet
9.3.3 Data Port register (address: 20h)
Table 38.
This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed
endpoint. The bit allocation is shown in
Peripheral-to-host (IN endpoint): After each write action, an internal counter is auto
incremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in
the TX FIFO. When all bytes are written (FIFO byte count = endpoint MaxPacketSize), the
Bit
7 to 5 -
4
3
2
1
0
Symbol
CLBUF
VENDP
DSEN
STATUS Status Acknowledge: Only applicable for control IN or OUT.
STALL
Control Function register: bit description
Description
reserved.
Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The
RX buffer is automatically cleared once the endpoint is completely read. This bit
is set only when it is necessary to forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue the CLBUF
command two times. For details on clearing buffers, refer to
and ISP1761 clearing an IN buffer
Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint to
send on the next IN token. In general, the endpoint is automatically validated
when its FIFO byte count has reached endpoint MaxPacketSize. This bit is set
only when it is necessary to validate the endpoint with the FIFO byte count,
which is below endpoint MaxPacketSize.
Remark: Use either bit VENDP or register Buffer Length to validate endpoint
FIFO with FIFO bytes.
Data Stage Enable: This bit controls the response of the ISP1583 to a control
transfer. After the completion of the set-up stage, firmware must determine
whether a data stage is required. For control OUT, firmware will set this bit and
the ISP1583 goes into the data stage. Otherwise, the ISP1583 will NAK the data
stage transfer. For control IN, firmware will set this bit before writing data to the
TX FIFO and validate the endpoint. If no data stage is required, firmware can
immediately set the STATUS bit after the set-up stage.
Remark: The DSEN bit is cleared once the OUT token is acknowledged by the
device and the IN token is acknowledged by the PC host. This bit cannot be
read back and reading this bit will return logic 0.
This bit controls the generation of ACK or NAK during the status stage of a
SETUP transfer. It is automatically cleared when the status stage is completed,
or when a SETUP token is received. No interrupt signal will be generated.
0 — Sends NAK
1 — Sends an empty packet following the IN token (peripheral-to-host) or ACK
following the OUT token (host-to-peripheral)
Remark: The STATUS bit is cleared to zero once the zero-length packet is
acknowledged by the device or the PC host.
Remark: Data transfers preceding the status stage must first be fully completed
before the STATUS bit can be set.
Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for
isochronous transfers.
Remark: Stalling a data endpoint will confuse the Data Toggle bit about the
stalled endpoint because the internal logic picks up from where it is stalled.
Therefore, the Data Toggle bit must be reset by disabling and re-enabling the
corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in
the Endpoint Type register) to reset the PID.
Rev. 07 — 22 September 2008
Table
39.
(AN10045)”.
Hi-Speed USB peripheral controller
Ref. 5 “ISP1582/83
© NXP B.V. 2008. All rights reserved.
ISP1583
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