ISP1583BSGA ST-Ericsson Inc, ISP1583BSGA Datasheet - Page 16

• Manufacturer Part Number: ISP1583BSGA
• Description: IC USB CTRL HI-SPEED 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSGA

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1583BS-S; ISP1583BS-S

NXP Semiconductors
ISP1583_7
Product data sheet
8.6.1 NXP Parallel Interface Engine (PIE)
8.6.2 Peripheral circuit
8.6.3 HS detection
8.6.4 Isolation
8.6 NXP high-speed transceiver
8.7 NXP Serial Interface Engine (SIE)
The ISP1583 is a device that can initiate SRP.
In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel
bidirectional data interface. The functions of the HS module also include bit-stuffing or
de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.
To maintain a constant current driver for HS transmit circuits and to bias other analog
circuits, an internal band gap reference circuit and an RREF resistor form the reference
current. This circuit requires an external precision resistor (12.0 k
the analog ground.
The ISP1583 handles more than one electrical state, Full-Speed (FS) or High-Speed
(HS), under the USB specification. When the USB cable is connected from the peripheral
to the host controller, the ISP1583 defaults to the FS state, until it sees a bus reset from
the host controller.
During the bus reset, the peripheral initiates an HS chirp to detect whether the host
controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there
is an HS host connected, then the ISP1583 switches to the HS state.
In the HS state, the ISP1583 must observe the bus for periodic activity. If the bus remains
inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero
(SE0) condition on the USB bus. If an SE0 condition is detected for the designated time
(100 s to 875 s; refer to
Section 7.1.7.6), the ISP1583 switches to the HS chirp state to perform an HS detection
handshake. Otherwise, the ISP1583 remains in the FS state, adhering to the bus-suspend
specification.
Ensure that the DP and DM lines are maintained in a clean state, without any residual
voltage or glitches. Once the ISP1583 is reset and the clock is available, ensure that there
are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines.
Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1583
DP and DM lines, there is a possibility of the ISP1583 clocking this state into the internal
core, causing unknown behaviors.
The NXP SIE implements the full USB protocol layer. It is completely hardwired for speed
and needs no firmware intervention. The functions of this block include: synchronization
pattern recognition, parallel or serial conversion, bit-stuffing or de-stuffing, CRC checking
or generation, Packet IDentifier (PID) verification or generation, address recognition,
handshake evaluation or generation.
Rev. 07 — 22 September 2008
Ref. 1 “Universal Serial Bus Specification Rev.
Hi-Speed USB peripheral controller
1 %) connected to
© NXP B.V. 2008. All rights reserved.
ISP1583
2.0”,
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