ISP1583BSGA ST-Ericsson Inc, ISP1583BSGA Datasheet - Page 37

• Manufacturer Part Number: ISP1583BSGA
• Description: IC USB CTRL HI-SPEED 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSGA

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1583BS-S; ISP1583BS-S

NXP Semiconductors
ISP1583_7
Product data sheet
9.2.4.1 Session Request Protocol (SRP)
9.2.5 Interrupt Enable register (address: 14h)
The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing,
followed by V
pulsing.
The ISP1583 can initiate the B-device SRP by performing the following steps:
10. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG
11. Once bit BSESSVALID is detected, turn on the SOFTCT bit to start normal bus
The B-device must complete both data-line pulsing and V
Remark: When disabling OTG, data-line pulsing bit DP and V
cleared by writing logic 0.
This register enables or disables individual interrupt sources. The interrupt for each
endpoint can individually be controlled using the associated bits IEPnRX or IEPnTX, here
n represents the endpoint number. All interrupts can be globally disabled using bit
GLINTENA in the Mode register (see
An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the
USB bus. The interrupt generation depends on Debug mode settings of bit fields
CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0] in the Interrupt
Configuration register.
All data IN transactions use the Transmit buffers (TX), which are handled by bits
DDBGMODIN[1:0]. All data OUT transactions go through the Receive buffers (RX), which
are handled by bits DDBGMODOUT[1:0]. Transactions on control endpoint 0 (IN, OUT
and SETUP) are handled by bits CDBGMOD[1:0].
Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up
and high-speed status) can also be individually controlled. A bus reset disables all
enabled interrupts, except bit IEBRST (bus reset), which remains logic 1.
The Interrupt Enable register consists of 4 bytes. The bit allocation is given in
1. Set the OTG bit to start SRP.
2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG
3. Start data-line pulsing: set bit DP of the OTG register to logic 1.
4. Wait for 5 ms to 10 ms.
5. Stop data-line pulsing: set bit DP of the OTG register to logic 0.
6. Start V
7. Wait for 10 ms to 20 ms.
8. Stop V
9. Discharge V
register.
cleared.
enumeration.
BUS
BUS
BUS
pulsing: set bit VP of the OTG register to logic 0.
pulsing: set bit VP of the OTG register to logic 1.
BUS
pulsing. The A-device can detect either data-line pulsing or V
for about 30 ms: optional by using bit DISCV of the OTG register.
Rev. 07 — 22 September 2008
Table
24).
Hi-Speed USB peripheral controller
BUS
pulsing within 100 ms.
BUS
pulsing bit VP must be
© NXP B.V. 2008. All rights reserved.
ISP1583
Table
BUS
36 of 99
32.