ISP1583BSGA ST-Ericsson Inc, ISP1583BSGA Datasheet - Page 42

• Manufacturer Part Number: ISP1583BSGA
• Description: IC USB CTRL HI-SPEED 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSGA

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1583BS-S; ISP1583BS-S

NXP Semiconductors
Table 39.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Data Port register: bit allocation
9.3.4 Buffer Length register (address: 1Ch)
R/W
R/W
15
0
0
7
0
0
buffer is automatically validated. The data packet will then be sent on the next IN token.
When it is necessary to validate the endpoint whose byte count is less than
MaxPacketSize, it can be done using the Control Function register (bit VENDP) or the
Buffer Length register.
Remark: The buffer can automatically be validated by using the Buffer Length register
(see
Host-to-peripheral (OUT endpoint): After each read action, an internal counter is auto
decremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in
the RX FIFO. When all bytes are read, buffer contents are automatically cleared. A new
data packet can then be received on the next OUT token. Buffer contents can also be
cleared using the Control Function register (bit CLBUF), when it is necessary to forcefully
clear contents.
Remark: The delay time from the Write Endpoint Index register to the Read Data Port
register must be at least 190 ns.
Remark: The delay time from the Write Endpoint Index register to the Write Data Port
register must be at least 100 ns.
Table 40.
This register determines the current packet size (DATACOUNT) of the indexed endpoint
FIFO. The bit allocation is given in
The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint
MaxPacketSize register is written (see
required. After a bus reset, the Buffer Length register is made zero.
IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer
Length register is not significant. This register is useful only when transferring data that is
not a multiple of MaxPacketSize. The following two examples demonstrate the
significance of the Buffer Length register.
Bit
15 to 8 DATAPORT[15:8] data (upper byte)
7 to 0
Table
R/W
R/W
14
0
0
6
0
0
Symbol
DATAPORT[7:0]
Data Port register: bit description
41).
R/W
R/W
13
0
0
5
0
0
Rev. 07 — 22 September 2008
Description
data (lower byte)
R/W
R/W
DATAPORT[15:8]
12
DATAPORT[7:0]
0
0
4
0
0
Table
Table
41.
R/W
R/W
11
45). A smaller value can be written when
0
0
3
0
0
Hi-Speed USB peripheral controller
R/W
R/W
10
0
0
2
0
0
R/W
R/W
9
0
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1583
R/W
R/W
8
0
0
0
0
0
41 of 99