CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 8

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5-2. Pin Description (continued)
6. CPU Architecture
This family of microcontrollers is based on a high performance,
8-bit, Harvard architecture microprocessor. Five registers control
the primary operation of the CPU core. These registers are
affected by various instructions, but are not directly accessible
through the register space by the user.
Table 6-1. CPU Registers and Register Names
The 16-bit Program Counter Register (CPU_PC) allows direct
addressing of the full 8 Kbytes of program memory space.
The Accumulator Register (CPU_A) is the general purpose
register, which holds the results of instructions that specify any
of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
Document 38-08035 Rev. *N
Flags
Program Counter
Accumulator
Stack Pointer
Index
QFN
32
10
12
17
19
27
28
29
30
31
16
13
32
11
2
1
CPU Register
QSOP
12
16
13
24
4
3
2
1
–
–
–
–
–
–
–
–
SOIC
24
15
12
24
4
3
2
1
–
–
–
–
–
–
–
–
SIOC
12
18
3
2
1
–
–
–
–
–
–
–
–
–
–
9
CPU_F
CPU_PC
CPU_A
CPU_SP
CPU_X
PDIP
17
14
18
Register Name
8
7
6
–
–
–
–
–
–
–
–
–
–
SOIC
16
11
2
1
–
–
–
–
–
–
–
–
–
–
–
8
PDIP
16
15
12
6
5
–
–
–
–
–
–
–
–
–
–
–
P0.5/TIO0 GPIO Port 0 bit 5. Configured individually
P0.6/TIO1 GPIO Port 0 bit 6. Configured individually
Name
P0.7
V
Vcc
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SS
The Stack Pointer Register (CPU_SP) holds the address of the
current top of the stack in the data memory space. It is affected
by the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It is also affected by the SWAP
and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] globally enables or disables interrupts.
The user cannot manipulate the Supervisory State status bit [3].
The flags are affected by arithmetic, logic, and shift operations.
The manner in which each flag is changed is dependent upon
the instruction being executed, such as AND, OR, XOR, and
others. See
Alternate function Timer capture inputs or Timer
output TIO0
Alternate function Timer capture inputs or Timer
output TIO1
GPIO Port 0 bit 7. Configured individually
Not present in the 16 pin PDIP or SOIC package
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
Supply
Ground
Table 8-1 on page
CY7C63310, CY7C638xx
Description
13.
Page 8 of 86
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