CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 35

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-2. P1 Data Register (P1DATA) [0x01] [R/W]
Table 14-3. P2 Data Register (P2DATA) [0x02] [R/W]
Table 14-4. P3 Data Register (P3DATA) [0x03] [R/W]
Document 38-08035 Rev. *N
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 1 pins.
Bit 7: P1.7 Data
P1.7 only exists in the CY7C638xx.
Bit [6:3]: P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
Besides their use as the P1.6–P1.3 GPIOs, these pins are also used for the alternate function as the SPI interface pins. To
configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register
The use of the pins as the P1.6–P1.3 GPIOs and the alternate functions exist in all the enCoRe II parts.
Bit 2: P1.2/VREG
On the CY7C638x3, this pin is used as the P1.2 GPIO or the VREG output. If the VREG output is enabled (Bit 0
Table 19-1 on page 58
The VREG functionality is not present in the CY7C63310 and the CY7C63801 variants. A 1 μF min, 2 μF max capacitor is
required on VREG output.
Bit [1:0]: P1.1–P1.0/D– and D+
When the USB mode is disabled (Bit 7 in
the P1.0 and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins respectively.
If the USB Force State bit (Bit 0 in
This register contains the data for Port 2. Writing to this register sets the bit values to output on output enabled pins. Reading
from this register returns the current state of the Port 2 pins.
Bit [7:2]: Reserved Data [7:2]
Bit [1:0]: P2 Data [1:0]
P2.1–P2.0 only exist in the CY7C638(2/3)3.
This register contains the data for Port 3. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 3 pins.
Bit [7:2]: Reserved Data [7:2]
Bit [1:0]: P3 Data [1:0]
P3.1–P3.0 only exist in the CY7C638(2/3)3.
Read/Write
Read/Write
Read/Write
Default
Default
Default
Field
Field
Field
Bit #
Bit #
Bit #
P1.7
R/W
7
0
7
0
7
–
0
-
is set), a 3.3V source is placed on the pin and the GPIO function of the pin is disabled.
P1.6/SMISO
Table
R/W
6
0
6
0
6
–
0
-
19-1) is set, the state of the D– and D+ pins are controlled by writing to the D– and D+ bits.
Table 21-1 on page 59
P1.5/SMOSI
R/W
5
0
5
0
5
–
0
-
Reserved
Reserved
P1.4/SCLK
R/W
4
0
4
0
4
–
0
-
is clear), the P1.1 and P1.0 bits are used to control the state of
P1.3/SSEL
R/W
(Table 14-9 on page
3
0
3
0
3
–
0
-
P1.2/VREG
R/W
CY7C63310, CY7C638xx
2
0
2
0
2
–
0
-
40).
P1.1/D–
R/W
R/W
R/W
1
0
1
0
1
0
P2.1–P2.0
P3.1–P3.0
P1.0/D+
Page 35 of 86
R/W
R/W
R/W
0
0
0
0
0
0
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