CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 56

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-7. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W]
Table 17-8. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Document 38-08035 Rev. *N
Bit 7: GPIO Port 1 Interrupt Enable
0 = Mask GPIO Port 1 interrupt
1 = Unmask GPIO Port 1 interrupt
Bit 6: Sleep Timer Interrupt Enable
0 = Mask Sleep Timer interrupt
1 = Unmask Sleep Timer interrupt
Bit 5: INT1 Interrupt Enable
0 = Mask INT1 interrupt
1 = Unmask INT1 interrupt
Bit 4: GPIO Port 0 Interrupt Enable
0 = Mask GPIO Port 0 interrupt
1 = Unmask GPIO Port 0 interrupt
Bit 3: SPI Receive Interrupt Enable
0 = Mask SPI Receive interrupt
1 = Unmask SPI Receive interrupt
Bit 2: SPI Transmit Interrupt Enable
0 = Mask SPI Transmit interrupt
1 = Unmask SPI Transmit interrupt
Bit 1: INT0 Interrupt Enable
0 = Mask INT0 interrupt
1 = Unmask INT0 interrupt
Bit 0: POR/LVD Interrupt Enable
0 = Mask POR/LVD interrupt
1 = Unmask POR/LVD interrupt
The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and
when written clears all pending interrupts.
Bit [7:0]: Pending Interrupt [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register clears all pending
interrupts.
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
GPIO Port 1
Int Enable
R/W
R/W
7
0
7
0
Sleep Timer
Int Enable
R/W
R/W
6
0
6
0
Int Enable
INT1
R/W
R/W
5
0
5
0
GPIO Port 0
Int Enable
R/W
Pending Interrupt [7:0]
R/W
4
0
4
0
SPI Receive
Int Enable
R/W
R/W
3
0
3
0
SPI Transmit
Int Enable
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
Int Enable
INT0
R/W
R/W
1
0
1
0
Int Enable
POR/LVD
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R/W
R/W
0
0
0
0
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