CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 54

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-4. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Table 17-5. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]
Document 38-08035 Rev. *N
Bit 7: Enable Software Interrupt (ENSWINT)
0= Disable. Writing 0s to an INT_CLRx register, when ENSWINT is cleared, causes the corresponding interrupt to clear
1= Enable. Writing 1s to an INT_CLRx register, when ENSWINT is set, causes the corresponding interrupt to post.
Bit [6:0]: Reserved
Bit 7: Reserved
Bit 6: GPIO Port 4 Interrupt Enable
0 = Mask GPIO Port 4 interrupt
1 = Unmask GPIO Port 4 interrupt
Bit 5: GPIO Port 3 Interrupt Enable
0 = Mask GPIO Port 3 interrupt
1 = Unmask GPIO Port 3 interrupt
Bit 4: GPIO Port 2 Interrupt Enable
0 = Mask GPIO Port 2 interrupt
1 = Unmask GPIO Port 2 interrupt
Bit 3: PS/2 Data Low Interrupt Enable
0 = Mask PS/2 Data Low interrupt
1 = Unmask PS/2 Data Low interrupt
Bit 2: INT2 Interrupt Enable
0 = Mask INT2 interrupt
1 = Unmask INT2 interrupt
Bit 1: 16-bit Counter Wrap Interrupt Enable
0 = Mask 16-bit Counter Wrap interrupt
1 = Unmask 16-bit Counter Wrap interrupt
Bit 0: TCAP1 Interrupt Enable
0 = Mask TCAP1 interrupt
1 = Unmask TCAP1 interrupt
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
ENSWINT
Reserved
R/W
7
0
7
–
0
Reserved
R/W
6
–
0
6
0
GPIO Port 3
Int Enable
R/W
5
–
0
5
0
GPIO Port 2
Int Enable
R/W
4
–
0
4
0
PS/2 Data Low
Int Enable
Reserved
R/W
3
–
0
3
0
Int Enable
INT2
R/W
CY7C63310, CY7C638xx
2
–
0
2
0
Wrap Int Enable
16-bit Counter
R/W
1
–
0
1
0
Int Enable
TCAP1
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R/W
0
–
0
0
0
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